ECE 7650: Advanced Computer Architecture

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ECE 7650 Advanced Computer Architecture

• Chapter 9
• Exceptions
• Advanced RISC Machines
• ARM Ltd.

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Exceptions Overview

• Exceptions are generated by internal and external
  sources.
• Preservation of the processors state is
  partially done automatically and the rest must be
  done by the programmer.
• ARM has seven types of exceptions.
• For each exception, the processor runs in a
  special mode, called the privileged processor
  mode.
• The Vectors are not really vectors, because the
  contents of the vector addresses contain a branch
  instruction, which is used to branch to the
  exception routine (except for the FIQ vector,
  which can contain the handler itself).

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Exception Types
Exception Type Mode Normal Pseudo Vector Address High Pseudo Vector Address
Reset Supervisor 0x00000000 0xFFFF0000
Undefined Instruction Undefined 0x00000004 0xFFFF0004
Software Interrupt (SWI) Supervisor 0x00000008 0xFFFF0008
Prefect Abort Abort 0x0000000C 0xFFFF000C
Data Abort Abort 0x00000000 0xFFFF0000
IRQ (Interrupt) IRQ 0x00000018 0xFFFF0018
FIQ (Fast interrupt) FIQ 0x0000001C 0xFFFF001C
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The 6th Spot

• The vector address at 0x00000014 (or 0xFFFF0014)
  is not used
• It had been used in previous ARM version for the
  Address Exception vector.
• It is reserved for future use.

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Reset Exception Processing

• When Reset is asserted, the processor immediately
  stops processing the current instruction, and
  when the reset is released, the processor
  automatically performs the following
• R14_svc UNPREDICTABLE value.
• SPSR_svc UNPREDICTABLE value.
• CPSR40 0b10011. //Supervisor mode.
• CPSR5 0 //execute in ARM state.
• CPSR6 1 //disable FIQ.
• CPSR7 1 //disable IRQ.
• PC 0x00000000 or 0xFFFF0000.

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Undefined Instruction Exception Processing

• An undefined instruction exception occurs if the
  processor executes a coprocessor instruction, and
  no coprocessor acknowledges that it can execute
  the instruction.
• An undefined instruction exception occurs if an
  attempt to execute an instruction that is
  undefined.
• Undefined instructions can be used to
• Emulate (in software) a coprocessor
• That is not physically available in the system
  hardware.
• Emulate (in software) an instruction
• That is not part of the standard ARM instruction
  set.

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Undefined Instruction Exception Processing

• When an Undefined Instruction exception occurs,
  the processor automatically performs the
  following
• R14_und address of the instruction after the
  undefined instruction.
• SPSR_und CPSR.
• CPSR40 0b11011. //Undefined mode.
• CPSR5 0 //execute in ARM state.
• //CPSR6 is unchanged
• CPSR7 1 //disable IRQ.
• PC 0x00000004 or 0xFFFF0004.
• To return from and Undefined Instruction
  exception
• MOV PC,R14

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Software Interrupt Exception Processing

• The SWI instruction causes a Software Interrupt
  exception to occur.
• The SWI exception is typically used to call the
  operating system to request some function, such
  as general purpose IO.
• Also, the SWI instruction can be used to return
  control back to the OS upon completion of a user
  program.
• The SWI instruction includes a 24-bit immediate
  operand, which can be used by the OS to determine
  what operating system function is being requested.

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Software Interrupt Exception Processing

• When a software interrupt (SWI) exception occurs,
  the processor automatically performs the
  following
• R14_svc address of the instruction after the
  SWI instruction.
• SPSR_svc CPSR.
• CPSR40 0b10011. //Supervisor mode.
• CPSR5 0 //execute in ARM state.
• //CPSR6 is unchanged
• CPSR7 1 //disable IRQ.
• PC 0x00000008 or 0xFFFF0008.
• To return from and SWI exception
• MOV PC,R14

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Pre-fetch Abort Exception Processing

• The Pre-fetch Abort exception occurs
• If an invalid instruction is being executed by
  the processor.
• The instructions following a taken-branch
  instruction are marked invalid by the pre-fetch
  memory system.
• A breakpoint instruction is executed and there is
  no hardware breakpoint implementation.
• In this case the handler implements the
  breakpoint code.
• The Pre-fetch handler must determine the cause
  and appropriately branch to the corresponding
  handler.

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Pre-fetch Abort Exception Processing

• When a Pre-fetch exception occurs, the processor
  automatically performs the following
• R14_abt address of the instruction 4.
• SPSR_abt CPSR.
• CPSR40 0b10111. //Abort mode.
• CPSR5 0 //execute in ARM state.
• //CPSR6 is unchanged
• CPSR7 1 //disable IRQ.
• PC 0x0000000C or 0xFFFF000C.
• To return to the aborted instruction (assume the
  reason for the abort is fixed)
• SUBS PC,R14,4

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Data Abort Exception Processing

• When the processor is accessing data (load or
  store)
• if the memory system detects a problem
• the memory system will signal a A Data Abort
  exception
• And mark the data as invalid.

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Data Abort Exception Processing

• When a Data Abort exception occurs, the processor
  automatically performs the following
• R14_abt address of the instruction 8.
• SPSR_abt CPSR.
• CPSR40 0b10111. //Abort mode.
• CPSR5 0 //execute in ARM state.
• //CPSR6 is unchanged
• CPSR7 1 //disable IRQ.
• PC 0x00000010 or 0xFFFF0010.
• To return to the aborted instruction (assume the
  reason for the abort is fixed)
• SUBS PC,R14,8

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Interrupt Request (IRQ) Exception Processing

• The IRQ exception is generated externally by
  asserting the IRQ pin on the processor.
• The IRQ is maskable (CPSR7)
• The IRQ has a lower priority than the Fast
  Interrupt Request (FIQ)
• The current instruction is completed before the
  processor responds to the IRQ.

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Interrupt Request (IRQ) Exception Processing

• When a IRQ exception occurs, the processor
  automatically performs the following
• R14_irq address of the next instruction to be
  executed 4.
• SPSR_irq CPSR.
• CPSR40 0b10001. //IRQ mode.
• CPSR5 0 //execute in ARM state.
• //CPSR6 is unchanged
• CPSR7 1 //disable IRQ.
• PC 0x00000018 or 0xFFFF0018.
• To return from an IRQ exception
• SUBS PC,R14,4

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Fast Interrupt Request (FIQ) Exception Processing

• The FIQ exception is generated externally by
  asserting the FIQ pin on the processor.
• The IRQ is maskable (CPSR6)
• FIQ is intended to support low latency devices.
• Registers R8 to R12 are banked.
• Minimizes the overhead of context switching.

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Fast Interrupt Request (FIQ) Exception Processing

• When a FIQ exception occurs, the processor
  automatically performs the following
• R14_fiq address of the next instruction to be
  executed 4.
• SPSR_fiq CPSR.
• CPSR40 0b10001. //FIQ mode.
• CPSR5 0 //execute in ARM state.
• CPSR6 1
• CPSR7 1 //disable IRQ.
• PC 0x0000001C or 0xFFFF001C.
• To return from an FIQ exception
• SUBS PC,R14,4

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Exception Priorities
Priority Exception
Highest 1 Reset
2 Data Abort
3 FIQ
4 IRQ
5 Pre-fetch Abort
Lowest 6 Undefined InstructionSWI

• Undefined and SWI cannot occur at the same time.
• Undefined and SWI are required to have lower
  priority than Pre-fetch Abort, since the latter
  indicates an instruction is invalid.
• Data Abort has higher priority than FIQ to assure
  that Data Abort handler resolves the problem
  after a nested FIQ exception.