Using Memory to Cope with Simultaneous Transient Faults

1
Using Memory to Cope with Simultaneous Transient
Faults
Universidade Federal do Rio Grande do
SulPrograma de Pós-Graduação em Engenharia
Elétrica

• Authors

2
The Problem

• Due to the technology scaling, future (an actual)
  technologies will be heavily influenced by
  electromagnetic noise causing SEU and SET
  inducted errors
• The ocurence of multiple SEU and SET, which was
  not a problem in the past, must have to be
  considered
• We must guarantee robustness at lowest cost
• Some usual protection techniques like TMR and
  N-MR might not work properly

3
Motivations

• Memory comes with intrinsic protection against
  manufacturing errors (spare columns and spare
  rows)
• There are protection techniques with low area and
  latency overhead like Reed Solomon that can be
  applied

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Our Proposal

• Use Reed-Solomon protected memory to replace
  combinational circuit
• Reducing the area sensible to faults
• Reducing the SER (soft error rate) of the circuit

5
Outline

• Case Studies
• Results
• Conclusions
• Future Work.

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Replacing Combinational Circuit by Memory (ROM
memory)

• Example
• 4x4 bit multiplier
• Fully combinational

Fully memory
EXPENSIVE X
8 inputs and 8 outputs
28 x 8 2,048 bits
Memory
Input A
4
result
Input B
8
4
Total area 2,048 transistors considering 1
transistor per bit
Total area 304 transistors
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Replacing Combinational Circuit by Memory (ROM
memory)

• Example
• 4x4 bit multiplier
• Fully combinational

Lets Replace just some part of the circuit !!!
1 column
Area cost 512 transistors Latency 7 cycles
Total area 304 transistors
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Case Studies

• 4x4 bit multiplier

Two memory based solutions were proposed

• Column multiplier

• Line multiplier

These two solutions were compared with the TMR
and N-MR techniques.
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Case Studies
4 taps 8 bit FIR Filter
Memory based solution compared with the
combinational one
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Case Studies

• 4x4 bit multiplier
• Column Solution

Protected by RS code
Sensitive to Faults
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Case Studies

• 4x4 bit multiplier
• - Line Solution

Sensitive to Faults
Protected by RS code
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Case Studies

• 8-bits FIR Filter with 4 taps
• Just using memory
• Memory size
• 248 x 18 77 Gb

Protected by RS code

• Memory comb sol.
• Memory size
• 24 x 10 160 bits
• Latency 8 cycles

Sensitive to faults
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Fault Injection Process

• Fault injection Steps
• Run the circuit fault free with the 1st input
• Run the circuit with single event level 0 at
  the 1st gate
• Compare the fault free and the single event
  level 0 results to detect if the fault have
  propagated
• Run the circuit with single event level 1 at
  the 1st gate
• Compare the fault free and the single event
  level 1 results to detect if the fault have
  propagated
• Repeat the process for all gates
• Repeat the process for all inputs
• Repeat the process for double faults

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Results
The voter Is too big
4x4 Bit Multiplier Fault Rate Results for SINGLE
Fault Injection
3 x
7 x
2 x more area
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Results
4x4 Bit Multiplier Fault Rate Results for DOUBLE
Fault Injection
The voter Is too big
5 x
2 x
13 x
5 x
4 x more area
2 x more area
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Results
FIR Filter Fault Rate Results for SINGLE Fault
Injection
18 x
FIR Filter Fault Rate Results for DOUBLE Fault
Injection
3.5 x less area
22.5 x
3.5 x less area
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Conclusions

• This work showed that replacing combinational
  circuit by memory based circuit can be used to
  improve circuit reliability against single and
  double faults, with some penalties in area and
  computational time
• The presented technique, permits different memory
  based solutions with different costs and gains
• Results showed that 5-MR technique may not work
  as expected.

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Future Work

• Implement this technique using magnetic memory
  (no area overhead)
• Test the presented approach with different case
  studies
• Develop a tool that chooses between different
  memory based solutions, which best fit for each
  application
• Implement this technique to develop a memory
  based processor.

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Thank You !!!

• Questions ???

e-mails
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Fault Injection Process

• Tools
• 4x4 bit multiplier
• Caco-ps Cycle Accurate Configurable Power
  Simulator
• - combinational
• - column
• - line
• Synthesized solutions (for more than 100 gates
  failing)
• - TMR
• - 5-MR
• FIR Filter
• - combinational
• - memory based
• using Altera FPGA EP20K200EFC484-2X.