This Week

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DOH!
2
Week 7 Presentation (did we skip a week or
something)

• Sarat Shifter Basic Istr Decoding
• Rick Strapped for Cache
• Dave Registers/Branch/Datapath
• Andrew CPSR Handling

3
Shifter

• Status
• Shifter Instruction Wiring Complete
• General Carry In/Carry Out Wiring Complete
• Exception Logic/Wiring Complete
• Pre-Shift Logic Complete

4
Pre-Shift Logic

• 3 Cases
• Immediate Shift
• 32 bit data
• 5 bit shift amount
• Register Specified Shift
• 32 bit data
• 8 bit shift amount
• Rotate Immediate
• 8 bit data
• 4 bit shift amount

5
Immediate Shift

• 32 bit data in
• Compatible
• 5 bit shift amount
• Must extend to 8 bits with zeros as the three
  high bits

6
Register-Specified Shift
Excellent Smithers

• 32 bit data in
• Compatible
• 8 bit shift amount
• Compatible

7
Rotate Immediate

• 8 bit data in
• Musts extend to 32 bits, with zeros in positions
  8-31
• 4 bit shift amount
• Must extend to 8 bits with zeros as the two high
  bits and zero at the lowest bit

8
Shifter
9
Timing

• Timing delays in cache can cause big problems
• Needed to add another pipeline in for the cache
• Cache instruction fetch and decode
• Cache Cache controller

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This Past Week

• Register Selection
• Branch and Branch w/ Link
• Datapath Construction

13
Register Selection

• If the instruction doesnt have a particular
  register, that register selection is a dont
  care.
• Multiply has Rd and Rn swapped.
• Other static values can be fudged in.

14
Branch

• Branch w/ and w/o link are more common than I
  realized.
• Branch adds the offset (shifted left 2) to the
  PC.
• PC has already progressed 2 words by the time of
  write back.
• Link writes address of next instruction into R14.

15
execute output
Rd
Successful branch w/ link?
14
mux
mux
offset
8
Register Bank
R14


PC
mux

4
16
Datapath and Beyond

• Hooked up components
• Execute blocks, instruction decode, PSR, register
  bank, pipeline stages (d flip flops)
• Adding additional controls for more complex
  instructions
• Data hazard detection and data forwarding
• Cache and memory integration

17
Manipulating the CPSR

• Setting the FLAG bits (NZCV)
• Only have to worry about this for Mult / ALU
  instr
• NZCV bits are set in CPSR when s bit 1

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Manipulating the CPSR

• Only set flag bits if s bit is set to 1 and MUL
  or ALU
• Update CPSR w/ NZCV from ALU
• NZCV from Mult
• or feed back in old NZCV

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Idea for Implementation
Mult (NZCV)
ALU (NZCV)
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CPSR NZCV Handler
(3128)
Mult (NZCV)
ALU (NZCV)
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Additional CPSR Handling

• Focus on PSR transfer instructions
• MRS / MSR
• Currently designing logic for this

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For Next Week

• Finish Instruction Decoding
• Implement Pipeline
• Multicycle Control
• Finalize Datapath
• Run Test Instructions
• Aye Carumba!