Memory

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Memory

• ELEC 311
• Digital Logic and Circuits
• Dr. Ron Hayne
• Images Courtesy of John Wakerly and Prentice-Hall

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Read-Only Memory (ROM)

• Non-volatile

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Combinational Logic Functions

• 2-to-4 decoder with output polarity control

• Use ROM to store truth table

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Another Example

• 4 x 4 unsigned binary multiplication

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ROM Contents
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Internal ROM Structure

• Two-Dimensional Decoding (32K x 8 ROM)

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E(E)PROM Storage Matrix
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ROM Control Inputs

• Chip Select
• Output Enable

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ROM Timing

• tAA access time from address
• tACS access time from chip select
• tOE/tOZ output-enable/disable time
• tOH output-hold time

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Random Access Memory (RAM)

• Read/Write Memory
• Independent of bits location
• Volatile
• Static RAM (SRAM)
• Data remains stored as long as power applied
• Dynamic RAM (DRAM)
• Data must be refreshed periodically

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Static RAM (SRAM)

• Read
• Address, CS, OE
• DOUT
• Write
• Address, DIN
• CS, WE

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SRAM Cell

• D Latch
• Select (SEL)
• Write (WR)

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Internal SRAM Structure
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SRAM Timing (Read)

• tAA access time from address
• tACS access time from chip select
• tOE/tOZ output-enable/disable time
• tOH output-hold time

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SRAM Timing (Write)

• tAS/tAH address setup/hold time before/after
  write
• tCSW chip-select setup before end of write
• tWP write-pulse width
• tDS/tDH data setup/hold time before/after write

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Synchronous SRAM
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Dynamic Ram (DRAM)

• Store data on capacitor
• destructive read
• write-back
• refresh cycle

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SDRAM Internal Structure

• 4M x 4

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SDRAM Timing (Read)

• PRE precharge (bit line)
• ACTV row-address strobe and activate bank
• READ column address and read command

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SDRAM Timing (Write)

• PRE precharge (bit line)
• ACTV row-address strobe and activate bank
• WRITE column address and write command

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Summary

• ROM
• EEPROM
• RAM
• SRAM
• DRAM