TRIO2 Interconnect Modeling and Synthesis for Signal Integrity

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TRIO2Interconnect Modeling and Synthesis for
Signal Integrity

• Project Leader Prof. Lei He, LHE_at_EE.UCLA.EDU
• Authors Jun Chen, Kevin Lepak, Min Xu
• UCLA Electrical Engineering Department
• Los Angeles, CA 90095
• (Tools and references available at
  http//eda.ee.ucla.edu)

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Interconnect Design Closure ?Interconnect
Synthesis Global Routing

• Device locations and constraints
• Delay
• Power
• Signal integrity
• Skew
• ...

• Interconnect synthesis should be integrated with
  global routing for design closure

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TRIO PackageInterconnect Synthesis under RC
model

• Technology advances lead to the need for
  interconnect-driven design
• Interconnect optimization techniques for
  performance
• Topology optimization
• Buffer (repeater) insertion
• Device sizing, wire sizing and spacing
• TRIO Tree, Repeater, and Interconnect
  Optimization
• Reduce interconnect delay by up to 7x
• Installed at Intel, IBM, HP, Fujitsu, and

TRIO Performance Optimization under RC model
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Is TRIO Sufficient for DSM Design?

• Coupling capacitance becomes the dominant
  capacitance component
• Inductive coupling gains more significance
• Interconnect impedance is more than resistance
• Z ? R j?L where ? ? 1/tr
• On-chip inductance should be considered
• when ?L ? R due to smaller and quicker devices
• Coupling capacitance and inductance affect both
  delay and signal integrity
• Signal integrity is one (or THE) upcoming barrier
  of design closure

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Impact of Coupling Capacitance

• Coupling capacitance introduces significant delay
  variations, especially for local and intermediate
  interconnects

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Resistance vs Inductance
Length 2000, Width 0.8 Thickness 2.0,
Space 0.8
Ls and Lx for two parallel wires
R and ?L for a single wire

• Reactance due to inductance becomes comparable to
  resistance for global interconnects

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Impact of Inductance
no shielding
coplanar wave guide for inductance reduction

• Inductance introduces significant noise,
  especially for global interconnects

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TRIO2

• TRIO2 integrated toolset for interconnect
  modeling, analysis and synthesis for signal
  integrity under RC and RLC models
• RC and RLC extraction
• Table-based RC model (with process variations)
  DAC97, CICC99
• Table-based R and L model CICC99, DATE00,
  GVLSI01
• RC and RLC circuit model generation
• 3D full model based on PEEC and VPEC submission
• 2D cascade model and normalized model
  DATE00GVLSI01
• Worst-case noise/delay model
• Keff model, and Length scaled Keff model
  ISPD00, ICCAD02
• Five-pole model, Decoupling model, WCN model, and
  t-line model DAC01, GVLSI02, ASP-DAC03
• Interconnect synthesis
• Shield insertion for buses and clocks CICC99
• Simultaneous shield insertion and net ordering
  ISPD00, DAC01
• Power net and shielding co-design ICCAD01
• Clock synthesis (buffering and shielding to
  control noise and rising time)

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SINO ISPD00, DAC00, ICCAD01Simultaneous
Shield Insertion and Net Ordering

• Given A set of signal nets, sensitivity, and
  noise bound
• Assume Shields can be assigned to arbitrary
  tracks or uniform shielding with minimal
  perturbation
• Find An SINO solution such that
• Capacitive noise free
• No sensitive wires are adjacent
• No neighboring wires switch simultaneously
• Inductive noise less than the given noise bound
• Minimal area

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SINO Experiment
Noise Bound Average number of shields Average number of shields Average number of shields Average number of shields
Noise Bound NOSI SINO NOSI SINO
Noise Bound Sensitivity Rate 30 Sensitivity Rate 30 Sensitivity Rate 60 Sensitivity Rate 60
0.15V 7.0 5.4 (-23) 10.8 7.85 (-30)
0.20V 6.15 5.05( -14) 10.6 7.45 ( -30)
0.25V 6.00 4.2(-30) 9.75 7.4(-33)

• SINO achieves up to 33 shield reduction compared
  to best alternative (NOSI)
• 32-bit signal bus, 2000 um long wire, in 70nm
  technology

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PWL Model for CPW

• Piece-Wise Linear model computes the far end
  response for a CPW with capacitive loading and
  ramp input
• CPW coplanar wave guide

Transform CPW to transmission line without
loading by moment matching
Construct the waveform for step input of
transmission line by 3-piece linear approximation
for each round trip of waveform
Construct the waveform for ramp input by over
3-piece approximation per round trip
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PWL versus SPICE
setting runtime runtime runtime runtime
model SPICE PWL work3 work4
1 88.1 0.01 0.01 0.18
2 148.1 0.01 0.01 0.18
3 368.23 0.01 0.01 0.12
4 23.23 0.01 0.01 0.73
5 121.39 0.01 0.01 0.2
6 344.7 0.01 0.01 0.02

• PWL obtains highly accurate waveform in 1000x
  less time
• 4 and 5 (Meindl00 and Eo02) have much
  bigger errors

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CPW Synthesis for Buffered Clock Tree
a x1 w1 s1 g1 x2 w2 s2 g2 power
0 237 1.5 4.4 8.2 149 1.1 5.0 10.7 1769ff
0.3 288 1.7 2.9 3.9 166 1.2 2.4 6.3 1899ff
1 500 4.8 3.2 2.1 324 1.4 1.5 2.1 2952ff

• Tradeoff between area and power
• Primarily decided by buffer size
• Min-power solution costs 3x area than min-area
  solution, but 2x less power
• Desired solution with a0.3
• Save 42 area with 4 more power compared to
  min-power solution
• a weighting factor to decide area/power
  tradeoff

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Overall Design Closure for Signal Integrity ?
TRIO2 Gsino VPEC

• Iterative ECO flow
• Circuit modeling and analysis of critical nets
  (TRIO2)
• Correction by net-based TRIO2/Gsino
• One-pass correctness by construction
• Chip-level Gsino w/ embedded TRIO2 and VPEC
• Gsino global routing with simultaneous shielding
  and net ordering
• VPEC vector potential equivalent circuit model,
  provably passive and 1000x faster than PEEC