NSS NSB Brief

1
Simulation Sciences Division High Performance
Computing
SPEEDESSynchronous Parallel Environment for
Emulation and Discrete-Event Simulation
2
Overview of SPEEDES

• METRON Simulation Sciences product since 1996
• Powerful optimistic-processing parallel
  processing engine
• Simulation events are distributed over multiple
  processors
• Events assigned to a processor proceed
  optimistically (i.e. assuming that processing on
  other nodes wont invalidate)
• When messages from one node invalidate processing
  on other nodes, incorrect processing is rolled
  back, invalid messages recalled, and are
  corrected
• Result as long as enough processors are
  available, speed and complexity of simulation is
  not limited
• Processing overhead (typically 15) associated
  with rollback/callback/reprocessing is generally
  not affected by number of processors
• Parallel-processing simulations mimic real-life,
  where most events happen independently in parallel

3
SPEEDES Development and Use

• Developed, maintained, and distributed by METRON
• Development funded by Joint National Integration
  Center (JNIC) and Air Force Research Laboratory
  (AFRL)
• Metron supplies source code to qualified (U.S.
  only) users at no charge
• On-line documentation and change request system
• Primary users
• JNIC Missile Defense Wargaming and Analysis
  Resource (MDWAR)
• Air Force Research Lab Joint Battlespace
  Infosphere Simulation (JBISim)
• Current Development Projects
• JNIC Multiple-simulation clusters (to add
  THAADS, Patriot, Airborne Laser, Aegis, etc.)
• AFRL Multiple parallel course-of-action
  simulation capability (Phase II SBIR)

4
Key SPEEDES Developers
Ron Van Iwaarden PhD, Applied Mathematics,
University of Colorado MS, Applied Mathematics,
University of Colorado BS, Mathematics,
University of Colorado SPEEDES developer for 8
years Lead, SPEEDES development and
documentation MDWAR wargame support at the
JNIC
Gary Blank MS, Comp. Science, University of
Virginia BS, Applied Mathematics, Brown
University SPEEDES developer for 8 years Lead,
SPEEDES Multi-COA Enhancement project SPEEDES
enhancements for MDWAR SPEEDES support of AFRL
(DIEMS, GIEsim) SPEEDES FAAsim prototype HLA
RTI developer HLA Federations
Jacob Burckhardt BS, Computer Science, UC
Berkeley SPEEDES developer for 8 years Lead,
JSIMS sim engine IVV SPEEDES enhancements for
MDWAR SPEEDES testing SPEEDES Configuration
Management
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SPEEDES Funding
(thousands of dollars)
1.0
2.0
2.1
2.2
Version
6
Competition

• SPEEDES maturity and performance puts it at the
  head of the pack
• Only optimistic parallel-processing engine
  receiving significant DoD funding
• RAM Labs has WARP IV derivative, with no known
  users
• Two MDA Phase II SBIRs starting
• Georgia Tech Time Warp
• Used in simulation of communication networks

7
The Future

• SPEEDES growth at the JNIC
• The Missile Defense program was severely
  chastised by the for its lack of quality
  simulations by Defense Science Board
• MDWAR was held up as the sole example of success
• The future for MDA is Ballistic Missile Defense
  System (BMDS) sim
• Decision isnt final, but it appears that MDWAR
  will be enhanced to become the BMDS sim
• Expectation is that METRON will receive at least
  a moderate amount of additional development work
• For AFRL, Phase II SBIR will lead to dramatic new
  simulation capability
• Northrop Grumman and Lockheed Martin are
  candidates for Phase III sponsorship

8
Conclusion

• SPEEDES is excellent choice for all parallel
  simulations
• Development on SPEEDES continues although at a
  slower pace
• Future is bright for BMDS simulation
• Should bring additional funding such as
  clustering or HLA capability
• Multiple course-of-action capability should make
  SPEEDES of interest to more clients
• The JNIC and AFRL continue to provide stable and
  consistent funding