shobha_shankaryahoo'com

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PROGRAMMABLE LOGIC DEVICES
shobha_shankar_at_yahoo.com
SHOBHA K.R MSRIT
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ORGANISATION

• INTRODUCTION TO PLD
• ROM BASICS
• IMPLEMENTATION OF BCD TO EXCESS-3
• CODE CONVERTER USING ROM
• PLAs BASICS
• IMPLEMENTATION OF BCD TO EXCESS-3
• CODE CONVERTER USING PLAs

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ROM BASICS

• Definition
• ROM consists of an array of semiconductor devices
  interconnected to store an array of memory data.
  Data can be only read, it cannot be changed under
  normal operating conditions.
• TYPES OF ROM.
• Mask programmable ROM
• Erasable programmable ROM (EPROM)
• Electrically erasable PROM (EEPROM)
• Flash

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BASIC ROM STRUCTURE
Eg4 x 8 ROM has 2 I/p Address lines. ---Can
store 4 words each of 8 bits
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IMPEMENTATION OF BCD TO EXCESS-3 CODE CONVERTOR
USING D F/F AND COMBINATIONAL CIRCUIT
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IMPEMENTATION OF BCD TO EXCESS-3 CODE CONVERTOR
USING D F/F AND ROM
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REALIZATION OF ROM TRUTH TABLE FROM STATE TABLE
OF BCD TO EXCESS-3
State table
ROM truth table
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STATE DIAGRAM FOR ROM
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VHDL CODE FOR BCD TO EXCESS-3 USING ROM contd..

• library bitlib
• use bitlib.bit_pack.all
• entity rom1_2 is
• port (x , clk in bit z out bit)
• end rom1_2
• architecture rom1 of rom1_2 is
• signal q, qplus bit_vector(1 to 3) "000"
• type rom is array (0 to 15) of bit_vector(3
  downto 0)
• constant fsm_rom rom
• ("1001","1010","0000","0000","0001","0000","0000",
  "0001",
• "1111","1100","1100","1101","0111","0100","0110","
  0111")

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VHDL CODE FOR BCD TO EXCESS-3 USING ROM

• begin
• process(q,x) --
  determines the next state and output
• variable romvalue bit_vector(3 downto 0)
• begin
• romvalue fsm_rom(vec2int(q x)) --
  read rom output
• qplus lt romvalue(3 downto 1)
• z lt romvalue(0)
• end process
• process(clk)
• begin
• if clk'1' then q lt qplus end if
  -- update state register
• end process
• end rom1

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PROGRAMMABLE LOGIC ARRAYS(PLAs)
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N-MOS PLA WITH 3 INPUT, 5 PRODUCT TERMS, AND 4
OUTPUTS
F0Sm(0,1,4,6) ABAC
F1Sm(2,3,4,6,7) BAC
F2Sm(0,1,2,6) ABBC
F3Sm(2,3,5,6,7) ACB
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AND-OR ARRAY EQUIVALENT OF NMOS 3INPUT 5PRODUCT
TERMS AND 4 OUTPUTS
PLA table
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REALIZATION OF PLA FOR A GIVEN EQUATION
F1 Sm(2,3,5,7,8,9,10,11,13,15) BDBCAB F2
Sm(2,3,5,6,7,10,11,14,15) CABD F3
Sm(6,7,8,9,13,14,15) BCABCABD
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REALIZATION OF PLA FOR A GIVEN EQUATION
F1 bd(aa) bc ab(cc) abd
abd bc abc abc
F2 c(bb) abd
bc bc abd
F3 bcabcabd

Reduced PLA table
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REALIZATION OF PLA FOR A GIVEN EQUATION
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PLA TABLE FOR BCD TO EXCESS-3
Reduced Equations
PLA Table
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VHDL CODE FOR BCD TO EXCESS-3 USING PLAs
library ieee use ieee.std_logic_1164.all --
ieee standard logic package library mvllib --
includes plamtrx type and use mvllib.mvl_pack.all
-- plaout function entity pla1_2 is port ( x ,
clk in std_logic z out std_logic) end
pla1_2 architecture pla of pla1_2 is signal q,
qplus std_logic_vector ( 1 to 3)
"000" constant fsm_pla plamtrx (0 to 6 , 7
downto 0) ("x0xx1000","1xxx0100","111x0010","1x
000010", "00x10010","xx000001","xx110001")
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VHDL CODE FOR BCD TO EXCESS-3USING PLAs
begin process (q,x) variable plavalue
std_logic_vector(3 downto 0) begin plavalue
plaout(fsm_pla,q x) -- read pla output qplus
lt plavalue (3 downto 1) z lt plavalue(0) end
process process(clk) begin if clk'1' then q lt
qplus end if -- update state register end
process end pla
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WAVEFORMS FOR BCD TO EXCESS-3 USING PLA
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VHDL CODE TO CREATE LIBRARY MVLLIB
library ieee use ieee.std_logic_1164.all package
mvl_pack is type plamtrx is array(integer
rangeltgt, integer rangeltgt) of std_logic function
plaout(plaplamtrx inputstd_logic_vector) return
std_logic_vector end package
mvl_pack package body mvl_pack is function
plaout(plaplamtrx inputstd_logic_vector)
return std_logic_vector
is variable matchstd_logic variable placol,
step integer
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VHDL CODE TO CREATE LIBRARY MVLLIB
variable plarow std_logic_vector((plalength(2)-1
) downto 0) variable plainp std_logic_vector((in
putlength-1) downto 0) variable output
std_logic_vector((plalength(2)-inputlength-1)
downto 0) begin output (othersgt 0) if
plaleft(2) gt plaright (2) then step -1 else
step 1 end if lp1 for row in plarange loop
--scan each row of pla match 1
placolplaleft(2) lp2 for col in
plarowrange loop -- copy row of pla
table plarow(col) pla(row,
placol) placol placolstep end
loop lp2
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VHDL CODE TO CREATE LIBRARY MVLLIB
plainp plarow(plarowhigh downto
plarowhigh-inputlength1) lp3 for col in
inputrange loop if input(col) /
plainp(col) and plainp(col) / X then match
0 exit end if end loop lp3 if match
1 then output output or
plarow(outputrange) end if end loop
lp1 return output end plaout end package body