MILESTONE 11

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MILESTONE 11 LVS Simulation
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STATUS

• Design Proposal (Done)
• Architecture (Done)
• Size Estimates/Floorplan/Verilog (Done)
• Gate Level Design (Done)
• Testing of Top-Level Schematic (Done)
• LVS of Entire Chip (98)
• LVS of FP Adder (Done)
• LVS of FP Multiplier (Done)
• LVS of Delay for Comb (Done)
• Simulations (50)
• To Be Done
• Connect Few Remaining Bus Lines at Top Level
• Top Level Simulation
• Optimizations Add Buffers Reduce White Space

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DESIGN DECISIONS

• Modified Registers to Improve Testing
• Added Reset
• Vertically Stretched FP Adder
• Reduces need to use Metal4 to allow room for
  global routing along left side

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STRATEGY for TESTING CRITICAL PATH ESTIMATION

• Strategy for Testing
• Test the main components individually
• Floating Point Adder
• Floating Point Multiplier
• Comb
• Test the top level
• Simpler to more complex inputs
• Critical Path
• Currently determining, but believe its a
  particular path through the FP_Adder

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LAYOUT Delay (Comb)
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LAYOUT FP Adder
_at_()CDS LVS version 5.0.0 06/02/2003 2045
(intelibm5) Like matching is enabled. Using
terminal names as correspondence points.
Net-list summary for /afs/ece.cmu.edu/usr/nmarwaha
/cds/LVS/layout/netlist count 949 nets 3
9 terminals 1111 pmos 1111 nmos
Net-list summary for /afs/ece.cmu.edu/usr/nmarwaha
/cds/LVS/schematic/netlist
count 960 nets 39 terminals 11 cds_thru 111
1 pmos 1111 nmos Terminal correspondence
points 1 Alt0gt 2 Alt10gt
3 Alt11gt 4 Alt1gt 5 Alt2gt
6 Alt3gt 7 Alt4gt 8 Alt5gt 9 Alt6gt
10 Alt7gt 11 Alt8gt 12 Alt9gt
13 Blt0gt The net-lists match. .
It LVSd!
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LAYOUT FP Multiplier
_at_()CDS LVS version 5.0.0 06/02/2003 2045
(intelibm5) Like matching is enabled. Using
terminal names as correspondence points.
Net-list summary for /afs/ece.cmu.edu/usr/nmarwaha
/cds/LVS/layout/netlist count 1068 nets
37 terminals 1232 pmos 1232 nmos
Net-list summary for /afs/ece.cmu.edu/usr/nmarwaha
/cds/LVS/schematic/netlist
count 1130 nets 39 terminals 62 cds_thru 12
32 pmos 1232 nmos Terminal
correspondence points 1 FP_1lt0gt
2 FP_1lt10gt 3 FP_1lt11gt 4 FP_1lt1gt
5 FP_1lt2gt 6 FP_1lt3gt 7 FP_1lt4gt
8 FP_1lt5gt 9 FP_1lt6gt 10 FP_1lt7gt
11 FP_1lt8gt 12 FP_1lt9gt
13 FP_2lt0gt The net-lists match.
It LVSd!
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FLOORPLAN Last Week
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TOP LEVEL LAYOUT - Current
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SIZE ESTIMATES

• Transistor Count 33,654
• Area 423x429 µm (181,467 µm2)
• Density 0.185
• Aspect Ratio 11

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VERIFICATION Top Level

• Verified all of the functions for the Swiss Army
  Knife in Schematic.
• Plotted outputs using custom made code MatLab.
• From plots it is evident that the accuracy is
  excellent.

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SIMULATIONS FP Adder
ExtractedRC Rise Time / Fall Time 1.5ns
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SIMULATIONS FP Mult
ExtractedRC Rise Time / Fall Time 1.5ns /
500ps
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PROBLEMS QUESTIONS

• Buffering Need to Reduce Rise/Fall Times
• Need to Reduce White Space
• Improve Density
• Verified Design Applications of Both Circuits
  (w/ w/o Complex Numbers - Soft IP) w/ DSP TA