Optimize Your SAR ADC Design

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Optimize Your SAR ADC Design

• Bonnie Baker
• Senior Applications Engineer
• bonnie_at_ti.com

Special Thanks for Inputs from Tim Green Rick
Downs Miro Oljaca
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SAR ADC System Design
SAR
OpAmp Signal Bandwidth Slew Rate Output
Impedance
Filter Charge Reservoir Capacitor Load
Isolation Noise Filtering
ADC Acquisition Time Data Rate Resolution ADC
Input Topology ADC Ref In
3
The Design Tools We Will Use

• Data Sheet Parameters .
• Rules of Thumb .
• Tricks and Tips .
• Testing .

4
Design Procedure
V
V
CC
REF
Op Amp
A/D
Filter
-
D
OUT
0 V
C

FLT
R
FLT
V
S
5
1. Define Input Signal
VCC
VREF
Op Amp

• Highest Frequency
• 1 kHz (single channel)
• Largest Voltage Swing
• 0 to 4.096 V
• High Accuracy
• 62.5 mV LSB size or 16-bit with range of 4.096

A/D
Filter
-
DOUT
0 V
CFLT

RFLT
VS
6
2. Selecting the ADC

• Things we need to know
• Sampling frequency gt 50 ksps
• Full-scale input range (FSR) 4.096V
• Highest Resolution 16-bit
• SAR Architecture no latency

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ADS8320 Application Specs

• 16-bit, 100 kHz Micropower, Sampling
  Analog-To-Digital Converter
• Throughput Rate (Sampling Rate) 100 ksps
• tACQ (min) 1.88 µs
• Input VFSR VREF 4.096 V
• CSH (input sample hold capacitance) 45 pF
• Secondary specifications
• SNR 88 dB _at_ 1 kHz
• THD -86 dB _at_ 1 kHz
• SINAD 84 dB _at_1 kHz
• SFDR 86 dB _at_1 kHz

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A/D Converter Terms

• Acquisition Time (tACQ)
• The time the internal A/D sample capacitor is
  connected to the A/D input analog signal
• Conversion Time (tCONV)
• The time the A/D requires to convert the sampled
  analog input to a digital output after the
  acquisition time (tACQ) is complete
• Throughput Rate Sampling Rate
• Maximum frequency at which A/D conversions can be
  repeated
• Is equal to the Acquisition time plus the
  Conversion time (tACQ tCONV)
• i.e. 100 ksps Throughput Rate Sampling Rate
  implies that an input analog signal may be
  converted every 10µs

9
SAR Acquisition and Conversion Time
S1
10
Single-pole, Time Constant Multiplier
11
ADC System Model
A/D
RFLT
RSW
?
100W
CSH
S1
CFLT
20pF- 50pF
VS
?
S2
12
SAR ADC Input Charge Distribution

• Op amp requirements
• Must charge the ADC cap quickly accurately

ADS8361
13
ADC Conclusion

• Key ADC specifications per Input Signal
• Sampling Rate 100 ksps
• Full-scale input range 4.096 V
• In following discussion we will use the ADS8320
• tACQ ADC acquisition time
• CSH ADC input capacitance
• k 16-bit time constant multiplier
• VFSR Full-scale input range of ADC

14
3. Choosing CFLT
VCC
VREF
Op Amp

• Provides charge to ADC sampling capacitor, CSH
• CFLT is the charge reservoir

A/D
Filter
-
DOUT
0 V
CFLT

VS
15
ADC Specs for CFLT Determination
tACQ
ADS8320

• Need to Know CSH, tACQ, k, VFSR
• tACQ 1.88 ms
• CSH (sampling ADC input capacitor) 45pF
• k 12
• Worst case ?V across CSH is VFSR
• VFSR VREF 4.096 V

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Capacitor Charge Transfer

• Prior to acquisition VIN ¹ VSH
• During acquisition
• CFLT and CSH exchange charge
• VSH changes to equal VIN

VIN
Charge Reservoir
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Ideal Value for CFLT

• Charge Transfer Equation Q C x V
• QSH CSH x VFSR
• QSH 45pF x 4.096V 184pC
• IDEAL CFLT
• Charge reservoir fills CSH with 1/2LSB from VS
  droop on CFLT
• 1/2LSB of VFSR VFSR / 2N (worst case)
• 1/2LSB of VFSR 4.096 V / 216 31.25 µV
• QSH QFLT
• QFLT CFLT x (1/2LSB from FSR)
• 184pC CFLT x (31.25µV) ? CFLT 5.9 µF

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IDEAL CFLT 5.9 µF Assessment

• The Driving Op Amp probably
• Can not directly drive a 5.9 mF capacitor
• Circuit may be marginally stable
• Could have transient current problems
• With resistor between Op Amp and capacitor
• Resistor and capacitor still need to meet signal
  bandwidth
• Resistor may not be large enough to help isolate
  CFLT

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CFLT Suggested Modification

• Starting Point Partition the charge reservoir
• 95 from CFLT
• 5 from Op Amp
• CFLT value provides QSH with lt5 droop on CFLT
• QFLT QSH
• QFLT CFLT x (0.05 VFSR)
• 184pC CFLT x (0.05 x 4.096V) ? CFLT 898 pF
• Well use 1000pF or 1 nF
• Ensure CFLT ³ 20 x CSH
• During tACQ the Op Amp must be able to replace 5
  VFSR on CFLT

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Capacitor Voltage Coefficient

• Voltage coefficient causes distortion
• C C0 x (1bVCAP)
• Also has non-linear error proportional to
  frequency
• Voltage and frequency coefficients impact ADC
  distortion

Source Murata
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Capacitor THDN versus Frequency
-60
-65
-70
-75
-80
-85
THD N (dB)
System Measurement
-90
-95
-100
-105
-110
200
500
1k
20k
50k
10k
10k
2k
5k
200k
100
Silver Mica
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CFLT Type and Value Requirements

• For our example CFLT 1 nF
• High quality capacitor
• Low Voltage Coefficient
• Low Frequency Coefficient
• Capacitor Type C0G
• CFLT gt 20 x CSH
• gt95 of Charge to ADC from CFLT
• lt 5 of Charge to ADC from OPA
• Dominant load of Op amp is CFLT
• Droop on CFLT lt 5

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4. Choosing RFLT
VCC
VREF

• Things we need to know
• tACQ ADC acquisition time (1.88 ms)
• k Single-pole time constant multiplier for
  16-bit ADC (12)
• CFLT External input capacitor to ADC (1 nF)

Op Amp
A/D
Filter
-
DOUT
0 V
CFLT

RFLT
VS
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First Pass Determination of RFLT Value

• First Pass RFLT Calculation
• tFLT RFLT x CFLT Filter time constant
• tACQ ³ k x tFLT
• 1.88 ms 12 x tFLT
• ? tFLT 157 ns

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RFLT Value with 40 Margin

• Given tACQ ³ k x tFLT
• Design in a margin of 40
• 60 x tACQ k x tFLT
• Margin for
• Op Amp Output Load Transient
• Op Amp Output Small Signal Settling Time
• RFLT ³ (0.60 x tACQ ) / ( k x CFLT)
• RFLT ³ (0.60 x 1.88 ns)/(12 x 1 nF)
• ? RFLT ³ 94.2 ?
• Use RFLT 100?

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5. Choosing Op Amp
VCC
VREF

• Things we need to know
• RFLT External input resistor to ADC (100 W)
• CFLT External input capacitor to ADC (1 nF)
• tACQ ADC acquisition time (1.88 ms)

Op Amp
A/D
Filter
-
DOUT
0 V
CFLT

RFLT
VS
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Primary Op Amp Buffer Specs
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Secondary Op Amp Buffer Specs

• Total Harmonic Distortion (THD)
• Low Noise for 16-bit performance
• Closed Loop Gain Error
• Peak Output Current
• Input Cross-over Distortion

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OP Amp Buffer Application Specs

• Application
• Single Supply 5V
• Buffer NO CM Input Crossover
• Slew Rate to track 1kHz Input
• Wideband for good gain flatness 1kHz, G1
• Wideband for fast transient response to Noise
  Filter Transients
• Low Noise for 16 Bit performance
• RRIO for 65mV to 4.935V Input and Output on 5V
  Supply
• Best Industry Choice
• OPA363 or OPA364 (OPA363 with Shutdown feature)
• 1.8V, 7MHz, 90dB CMRR, Single-Supply,
  Rail-To-Rail I/O

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OPA363/OPA364 Application Specs

• SRMIN (V/µs) 2 p f x VOP (1e-6)
• Minimum Slew Rate to track input sine wave (_at_ lt1
  Distortion)
• SRMIN 2x p x 1kHz x (4.096Vpp/2) x (1e-6)
  0.013V/µs
• OPA363/OPA364 5V/µs
• Choose Op Amp SROPA gt 2 X SRMIN
• Gain Error
• ACL AOL/(1Aolß)
• AOL _at_1kHz 80dB 10000
• ß 1 for Unity Gain Follower
• ACL 10,000/(1100001) 0.99990001
• 0.009999 Gain Error _at_ 1kHz
• 12 Bit (1/2 LSB Accuracy)
• Calibrate gain error at system level
• Many systems are more concerned about relative
  changes than absolute

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Systems Transients

• Input Transient Load Transient
• Input Step Voltage Output Step Voltage
• Output Voltage Slew Rate Output Step Current

Line Transient
Load Transient
IT
OPA364
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Calculating the Op Amp Bandwidth

• Calculate Unity Gain BW
• Select Op Amp BW
• GBWP gt 4 X fFLT f-3db
• fFLT f-3db 1/2?RFLT x CFLT
• fFLT f-3db 1/2? x ?100W x 1 nF 1.6 MHz
• Op Amp GBWP gt4 x 1.6 MHz 6.4 MHz

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OpAmp Filter Small Signal
VFLT
VOA
ADS8320
-
RFLT
107 W
100 W

CFLT
1 nF
OPA364
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OpAmp Filter Frequency Response
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OpAmp Filter Stability

• Buffer Closed Loop Gain Bandwidth as modified by
  RFLTCFLT
• fCL 3.2 MHz
• Stability Check
• At fCL 3.2 MHz Rate-of-closure is 20dB/decade
  ? fZX cancels fPX before fCL
• fCL gt 2 x fFLT-3dB
• fPX and fZX are lt decade apart
• Phase of pole will be cancelled by phase of
  zero
• RO 9 x RFLT
• fFLT-3db 1/2?RFLT x CFLT 1.6MHz

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Amplifier Selection Guidelines

• Stability insured and Bandwidth exceeds input
  signal
• GBWP gt 4 x fS(MAX)
• GBWP ³ 2 / (p CFLT x RFLT)
• RO 9 x RFLT
• fCL gt 2 x fFLT-3dB
• Slews fast enough for the input signal
• SROPA gt 4p x fS(MAX) x VOP x (1e-6)

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Final OPA-SAR Circuit Design
VCC 5V
VREF 4.096V
VCC
RFLT 100W
-
IN
OPA364
Digital Out
ADS8320

- IN
CFLT 1 nF
VS
38
ADS8320 On Test System
ADS8320 SNR 88dB ENOB 14.33
Input Frequency 1kHz
Input Amplitude -0.25 dB
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OPA364 Filter ADS8320
Op Amp Filter ADS8320 SNR 87.78dB ENOB
14.19
Input Frequency 1kHz
Input Amplitude -0.25 dB
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Comparison of Tests
ADS8320 SNR 88dB ENOB 14.33
ADS8320 Only
OPA364, Filter, ADS8320
Op Amp Filter ADS8320 SNR 87.78dB ENOB
14.19
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Design Equations SAR-ADC System

• Filter Capacitor and Resistor Values
• CFLT gt 20 x CSH
• RFLT ³ (0.60 x tACQ ) / ( k x CFLT)
• Select Amplifier
• GBWP gt 4 x fS(MAX)
• GBWP ³ 2 / (p CFLT x RFLT)
• RO 9 x RFLT
• fCL gt 2 x fFLT-3dB
• SROPA gt 4p x fS(MAX) x VOP x (1e-6)

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Summary Design Steps
V
V
CC
REF
Op Amp
A/D
Filter
-
D
OUT
0 V

R
FLT
C
FLT
V
S
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REFERENCES

• Reference 1 Baker, B., Oljaca, M., Use External
  components to Improve the Accuracy of a SAR ADC,
  EDN 2007
• Reference 2 Green, Tim, Operational Amplifier
  Stability Part 3 of 15 RO and ROUT,
  AnalogZone Acquisition Zone
• Reference 3 Oljaca, M. and McEldowney, J.
  (2002.) Using a SAR Analog-to-Digital Converter
  for Current Measurement in Motor Control
  Applications. Burr-Brown Application Report
  SBAA081.
• Reference 4 Downs, R. and Oljaca, M. (2005)
  Designing SAR ADC Drive Circuitry Part II.
  AnalogZONE Acquisition Zone.
• Reference 5 Downs, R., Oljaca, M., Designing
  SAR ADC Circuitry Part 1 A Detailed Look at
  SAR ADC Operation, AnalogZone Acquisition Zone
• Reference 6 Downs, R., Oljaca, M., Designing
  SAR ADC Drive Circuitry Part 3 Designing the
  Optimal Input Drive Circuit for SAR ADCs,
  AnalogZone Acquisition Zone
• Reference 7 Green, T. (2005) Operational
  Amplifier Stability - Part 6 of 15
  Capacitance-Load Stability RISO, High Gain CF,
  Noise Gain AnalogZONE Acquisition Zone.
• Reference 8 Baker, Bonnie, A Glossary of
  Analog-to-Digital Specifications and Performance
  Characteristics, Texas Instruments, SBAA147

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Optimize Your SAR ADC Design