Delay Fault Avoidance Through Hierarchical Analysis of Process Variability

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Delay Fault Avoidance Through Hierarchical
Analysis of Process Variability

• Jennifer Miller
• 30 November 2004

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Outline

• Delay Faults
• Process Variability
• Project Goal
• Parameter Selection
• Hierarchical Circuit Model
• Statistical Algorithm
• Future Work

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Delay Faults

• Occur when circuit does not meet timing
  specifications
• Example from 254 lecture Processor meant to be
  clocked at 4 GHz has a slow path in the pipe that
  can only run at 3.8 GHz
• Design may be logically correct
• Can be very difficult to debug
• May be due to design, clock skew, clock jitter,
  environmental effects, etc.

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Process Variability

• Natural fluctuations in manufacturing processes
• Affects both geometrical and process-related
  parameters
• Geometry Transistor length, width
• Process dopant concentration, tOX

Device parameters, such as transistor length, are
actually normally distributed about a mean
dictated by statistical process control
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Why is variability a problem?

• Transistor dimensions shrinking rapidly
• Process control for small geometries is difficult
• Even if variability is constant between process
  generations, the effects will worsen

Process A Lmean 1 µm Ls 0.01 µm s percentage
of nominal 1
Process B Lmean 65 nm Ls 0.01 µm s percentage
of nominal gt15
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The Bottom Line on Variability

• Variability in the process may result in delay
  faults
• Effect of process variability on circuit delay
  must be quantified for use in the design process

Project Goal Develop an accurate and tractable
model for process variability for use in the
digital circuit design process
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Process Parameter Selection

• Drain current is a good measure of delay through
  a transistor
• Which parameters have an effect on delay?
• TOX
• W
• L
• VTN ? function of VTO
• ?

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Sensitivity Analysis

• Measure the percent change in delay associated
  with a small change in a process parameter
• Example Change L of the nFET in an inverter by
  2 and observe the percent change in fall time is
  1.5. Sensitivity of delay to L is then
  0.015/0.02 0.75
• Sensitivity 0 if the parameter has no effect on
  delay
• Conducted a sensitivity analysis on an inverter
  in SPICE with a 0.18µ model

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Sensitivity Analysis Results
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Circuit Model

• Hierarchical graph with 4 levels

Level 3 Paths from inputs(s) to output(s)
P1
P2
Level 2 Sub-paths
A
C
B
Level 1 Transistor Groups
T1
T3
T2
Level 0 Process Parameters
L1
W1
L2
W2
L3
W3
L4
W4
L5
W5
L6
W6
Each node has a µ and a s 2
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Circuit Model, cont.
A
out1
T3
B
C
in
T1
out2
T2
Level 3 Paths from inputs(s) to output(s)
P1
P2
Level 2 Sub-paths
A
C
B
Level 1 Transistor Groups
T1
T3
T2
Level 0 Process Parameters
L1
W1
L2
W2
L3
W3
L4
W4
L5
W5
L6
W6
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Statistical Algorithm

• To find the µ and a s 2 of the nodes on level
  n1 based on the µ and a s 2 of the nodes on
  level n
• Construct the sensitivity matrix, A, between the
  2 levels
• µn1 A µn
• Sn1 ASnAT

Based on fundamental principles of multivariate
normal statistics under the assumption that the
delay response to variability is linear.
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Example Finding the Mean
T1
T2
x1
x4
y1
y4
L1
W1
L2
W2
L3
W3
L4
W4
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Project Circuit
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Future Work

• Finish coding statistical algorithm in C and
  Matlab
• Automate SPICE sensitivity analysis
• Spatial correlation
• Apply model to real microprocessor circuits