D

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DØ RunIIb Trigger Upgrade

• Paul Padley
• for the DØ Trigger Upgrade Group

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This talk

• Will briefly review this (previously approved)
  upgrade
• Will give the current status of the major
  components of this upgrade
• Darien Wood will discuss future plans and cost to
  completion.

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The Run IIa Trigger System
Detector
Level 1
Level 2
7 MHz
2.5 kHz
1 kHz
CAL
L1Cal
L2Cal
c/f PS
L1PS
L2PS
CFT
L1CTT
L2CTT
SMT
L2STT
L1Mu
MU-TRK
MU
L2Mu
FPD
L1FPD
Global L2
Lumi
Framework
L3/DAQ
100 Hz
Level 3
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The Run IIb Trigger System
Detector
Level 1
Level 2
7 MHz
2.5 kHz
1 kHz
CAL
L1Cal
L2Cal
Cal-TRK
c/f PS
L1PS
L2PS
CFT
L1CTT
L2CTT
SMT
L2STT
L1Mu
MU-TRK
MU
L2Mu
FPD
L1FPD
Global L2
Lumi
Framework
New (or replaced) System
L3/DAQ
100 Hz
Level 3
Enhanced System
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Ingredients of the Trigger Upgrade L1 Cal

• Calorimeter trigger upgrade
• sharpens turn-on trigger thresholds
• more topological cuts
• cf simulation talk
• Largest subproject in the trigger upgrade
• Will require removing the existing Cal trigger

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Ingredients of the Trigger Upgrade CalTrack

• Exploit new L1Cal trigger
• Improve Run IIa f matching granularity x8
• Needed in triggers for Higgs searches
• electrons in WH and H WW modes
• taus in H tt and H tn
• Fake EM rejection is improved by x2
• Fake t rejection is improved by x10
• Upgrade modeled on existing Mu-Track match system
• Very few changes with respect to Mu-Track

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Ingredients of the Trigger Upgrade L1CTT

• Level 1 Central Track Trigger (CTT) essential for
  electrons, muons, taus (WH?l?jj)
• Tracking trigger rates sensitive to occupancy
• Upgrade stategy
• Narrow tracker roads by using individual fiber
  hits (singlets) rather than pairing adjacent
  fibers (doublets)
• Cal-track matching

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Ingredients of the Trigger Upgrade L1CTT

• Original idea was to simply replace FPGAs to
  newer larger ones that allow more equations
• Last year we upscoped the project to allow
  enhanced monitoring and debugging capability
• The project now involves replacing two crates of
  electronics
• All elements in this upgrade have been designed
  to minimize commissioning time and simplify
  debugging

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Ingredients of the Trigger Upgrade Level 2

• Level 2 STT expand system to allow for the new
  channels
• Level 2 Processors. Buy new faster processors to
  allow more functionality at this trigger level

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Management structure
WBS 1.2 Trigger Upgrade P. Padley (Rice), D.
Wood (Northeastern)
WBS 1.2.1 Level 1 Calorimeter M.Abolins(MSU),
H.Evans(Columbia)
Project is largely university based
WBS 1.2.2 Level 1 Cal-track match K. Johns
(Arizona)
WBS 1.2.3 Level 1 Tracking M. Narain (Boston),
Don Lincoln (FNAL)
WBS 1.2.4 Level 2 Beta upgrade R. Hirosky
(Virginia)
WBS 1.2.5 Level 2 STT upgrade U. Heintz (Boston)
WBS 1.2.6 Trigger Simulation M. Hildreth (ND),
E. Barberis (NEU)
WBS 1.2.7 AFE upgrade (Pending) A. Bross (FNAL)
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WBS 1.2.1 L1Cal
Clustering
ADCdigital filtering
Global sums topological
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L1Cal Hardware VME/SCL

• VME/SCL (Distributes VME and SCL for the TAB and
  GAB)
• working reliably for over a year
• No changes have been required in the board
• SCLD (Distributes SCL for the ADF system)
• Has been used successfully in integration tests.
• Both boards are complete

VMC/SCL
SCLD
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ADF Prototype V1
ADF Prototype board Underwent integration tests
at Fermilab, Oct 03 Was successfully operated
with D0 timing signals Sent data to TAB using D0
timing signals
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ADF V2

• ADF V2 Prototypes are in hand and being bench
  tested

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ADF V2

• 10 Cards received in January
• 4 cards fully stuffed and tested
• All 4 seem to work just fine
• VME connection . in good shape, doing everything
  needed .
• Analog ADC Section
• have been testing this heavily
• checking noise levels,
• cross talk,
• frequency response, etc.
• Output to TAB (Channel Link)
• SCL Connection
• All looks good. Production Readiness Review
  scheduled for Feb 11

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TAB

• Fully tested including
• All algorithmic functionality
• All input output functionality
• Data from ADF
• Data to Cal-Track
• Data to L2/L3
• Production boards are in hand and bench testing
  has finished

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GAB

• Production boards are in hand and bench testing
  has finished
• Both TAB and GAB are now undergoing long term and
  system tests

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TAB GAB rack under test
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L1Cal Summary

• All boards are in good shape
• TAB/GAB production complete
• Bench testing has finished, system testing begun
  
• ADF preproduction boards are in hand and are
  passing all tests.
• Production review in one week.

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L1CalTrack Trigger Overview
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Hardware Status

• SLDBs (Serial Link Daughter Boards)
• Production complete
• Testing complete
• MTCM (Crate Mananger)
• Production complete
• Testing 50 complete
• MTCxx (Trigger Card)
• Production versions in hand and testing is
  underway
• UFB (Flavor Board)
• Production will be assembled by Feb 11
• Splitter Cards
• Will be made soon

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Preproduction MTCxx with Prototype MTFB
UFB
SLDBs
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UFB
Gbit/s XMIT
Gbit/s RECV
Stratix FPGA
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Infrastructure Status

• L1Caltrack trigger and readout crates
• Installed and populated (using spare L1MU cards)
• Rack infrastructure (power, water, )
• 98 Complete, small mod needed
• VME crate power supply
• In hand, waiting for delivery of custom power
  leads
• Currently using spare L1MU supply
• Cables
• Collision hall to MCH1 cables complete
• L1CTT will be made in spring
• MTCxx cable termination complete

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L1CalTrack Summary

• A lot of the hardware has been produced
• The rest is currently in production.
• Testing is ongoing

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L1 Central Track Trigger

• Digital Front End Axial (DFEA) daughter cards
  redesigned with larger FPGAs (Xilinx Virtex-II
  XC2V6000)
• Allows more complicated equations for using
  narrower roads
• Implemented prototype firmware (Boston U)
• Includes equation files from all 4 momentum bins
• DFEA logic is implemented in two FPGAs
• Prototype board functionality tested
• Previously approved system design changes to make
  the upgrade easier to commission were made

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DFEA Board

• Preproduction boards in hand
• Have been tested on the bench and in the
  experiment
• PRR was held in January
• Need a couple more quick tests
• About to release for production

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Controller, Backplane and Splitters

• All Done, tested
• New backplane
• Controller
• LVDS Splitters Bare PC boards are now in hand

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CTT summary

• Things are progressing well
• About to go into full production of final boards

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Run 2B hardware summary
Run 2A Run 2A Run 2B I Run 2B I Run 2B II Run 2B II upgrade
system have system need system need baseline
FRC 6 7(10) 6 0 6 0 0
STC 54 64(80) 60 0 60 0 7
TFC 12 17 12 0 24 10 8
MB 72 100 78 0 90 10 20
BC 72 75(87) 78 30 90 30 20
LTB 78 134 84 0 114 20 52
LRB 90 144 96 0 132 20 46
hotlink 12 16 12 0 24 15 15
need to check how many work need to check how many work need to check how many work requires new hotlink merge card requires new hotlink merge card requires new hotlink merge card requires new hotlink merge card
Two different 2B scenarios compared to 2A and
baseline. 2B-I scenario chosen due to its
simplicity
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STT upgrade

• This upgrade is simply making more of the boards
  that are currently used to allow for the
  inclusion of layer 0
• Parts in danger of obsolescence have been
  procured
• Gaining experience from Run IIa
• PRR was held and production has begun
• Now only building Buffer Controllers

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L2 Beta Upgrade

• This is a simple replacement of CPUs in the L2
  system
• One candidate board (Concurrent Technology P220)
  was tested and rejected
• Adlink SBC tested and met requirement
• Board is compatible with future faster Intel
  processors

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Directors Review - Trigger

• Recommendations
• Secure the manpower for all installation needed
  in the 2004 shutdown to allow testing during the
  data taking of FY05.
• CF Simulation and SCIPC talks. Those are the
  areas where help was needed and much progress has
  been made
• Establish a forum (presumably through the
  Director for Research) for ongoing dialog with
  CDF and the Accelerator Division on the timing of
  the FY05 shutdown (maybe this exists already).
• Agreed. The director is aware of this.
• It would be helpful to have a presentation on the
  trigger simulation and validation efforts some
  time in early 2005.
• CF. simulation talk
• It would be useful to have a presentation of the
  SC-IPC task list around the same time.
• Cf. SCIPC talk

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Conclusions

• Outstanding progress has been made on all fronts.
• Lots of stuff is being built now and the rest is
  about to go into production
• It is an exciting time for the project as it
  starts to come together.