Aliases

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Topics

• Aliases
• Subprograms
• Generics Configurations

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Aliases

• An alternate name for name items

• Can significantly improve the readability of
  VHDL codes by using a shorthand notation for long
  names.

• Provides a mechanism to refer to the same named
  item in different ways.

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Aliases
An example
signal S BIT_VECTOR (31 downto 0)
Can represent
Sign Exponent Mantissa
31 30 23
0
Or
OP Reg Base
Offset
31 26 23 18
0
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Aliases

• Syntax

alias identifier identifier-type is
item-name
Optional signature portion
alias identifier identifier-type is
item-name signature
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Aliases

• Object aliases
• Constant
• Signal
• Variable
• File

• Non-Object aliases
• Function names
• Literals
• Type names
• Attribute names

Except labels, loop parameters, and generate
parameters
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Aliases
Object aliases
Examples
constant number_of_bytes integer 4 alias N
integer is number_of_byptes
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Aliases
Object aliases
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Aliases
Object aliases
We can avoid this by Introducing two alias
declarations into our model!
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Aliases
None-object aliases
Example
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Aliases

• With aliases, it is possible to declare
  something like subtypes, if the what we
  required is just a somewhat restricted version of
  the original type.

In this way, we break down complex data
structures into simpler parts that can be
accessed directly.
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Aliases
An example
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Aliases

• With aliases, it is possible to declare
  something like subtypes, if the what we
  required is just a somewhat restricted version of
  the original type.

In this way, we break down complex data
structures into simpler parts that can be
accessed directly.
Notice we are NOT defining a new data type.
However, there are real subtypes.
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Aliases

• Language Features SUBTYPES
• SUBTYPE TYPE constraints on values
• TYPE is the base-type of SUBTYPE
• SUBTYPE inherits all the operators of TYPE
• SUBTYPE can be more or less used interchangeably
  with TYPE
• examples

subtype small_float is real range 0.0 to 1.0
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Aliases

• Signature

alias identifier identifier-type is
item-name signature
The signature portion is optional.

• Used for
• Subprograms
• Enumeration literals

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Aliases

• Syntax

alias identifier identifier-type is
item-name signature
The signature portion is optional.
Signatures syntax rule
type_mark , return type_mark
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Aliases
None-object aliases
Example
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Topics

• Aliases
• Subprograms
• Generics Configurations

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Subprograms

• Like other programming languages, VHDL provides
  subprogram facilities in the form of functions
  and procedures.
• VHDL also provided a package facility for
  collecting declarations and objects into modular
  units.
• Packages also provide a measure of data
  abstraction and information hiding.

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Subprograms

• Two steps
• First they must be declared
• Then they can be called elsewhere.

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Subprograms
Modes
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Subprograms functions

• Functions
• Can be used within an expression
• Can be used to describe frequently used
  sequential algorithms
• Return a single value
• Execute in zero simulation time (no WAIT
  allowed).

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Subprograms functions
Declaration
pure impure function identifier (
parameter_interface_list ) return type_mark
is subprogram_declarative_item begin
sequential_statements end function
identifier
Where parameter_interface_list is
( constant variable signal identifier ,
in type_indication static_expression
) ,
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Subprograms functions

• Example

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Subprograms functions
Declaration
pure impure function identifier (
parameter_interface_list ) return type_mark
is subprogram_declarative_item begin
sequential_statements end function
identifier
Call
identifier (parameter_association_list )
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Subprograms functions

• Example

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Subprograms functions

• By default, functions are declared as pure
• In pure functions, the only accessible data are
  the input arguments and the only returned
  information from this function is the returned
  value. Pure functions do not have access to
  objects outside the function.

• VHDL93 introduces impure declaration
• Impure functions must be explicitly declared
• Impure functions can modify data outside their
  own scope.

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Subprograms functions

• Example

The file bit_file is an outside object. Since
the function is impure, accessing to the file
bit_file is possible.
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Subprograms functions

• Usages of functions
• Returning a value in an expression.
• Conversion functions.
• ------ to convert an object of one type to
  another
• Resolution functions.
• ------ to resolve bus contention on a
  multiply-driven signal

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Subprograms functions

• Conversion functions.
• are used to convert an object of one type to
  another to allow mapping of signals and ports of
  different types. This type of situation usually
  arises when a designer wants to make use of an
  entity from anther design that uses a different
  data type.

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Subprograms functions

• Resolution functions
• are used to return the value of a signal when
  the signal is driven by multiple drivers. It is
  illegal in VHDL to have a signal with multiple
  drivers without a resolution function attached to
  it.
• A resolution function has a signal-argument
  input (consists of an unconstrained array of
  driver values for the signal) and returns a
  single signal value.

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Subprograms procedures

• Procedures
• Can be used to partition large behavioral
  descriptions into modular sections
• A procedure call may be a sequential or
  concurrent statement
• Arbitrary number of parameters of any possible
  direction ( in / out / inout )
• May or may not execute in zero simulation time.

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Subprograms procedures
Declaration
procedure identifier ( parameter_interface_list
) is subprogram_declarative_item begin
sequential_statements end procedure
identifier
Where parameter_interface_list is
( constant variable signal identifier ,
mode type_indication static_expression
) ,
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Subprograms procedures
Declaration
procedure identifier ( parameter_interface_list
) is subprogram_declarative_item begin
sequential_statements end procedure
identifier
Call statement
label procedure_name (parameter_associatio
n_list)
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Subprograms procedures
Example
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Subprograms procedures
Default Values in the parameters When the
procedure is called, we can use either leave it
out in the callers parameter list, or use
keyword open.
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Subprograms procedures
Example
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Subprograms procedures
Declaration
procedure identifier ( parameter_interface_list
) is subprogram_declarative_item begin
sequential_statements end procedure
identifier
Call statement
label procedure_name (parameter_associatio
n_list)
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Subprograms procedures
Concurrent Procedure Call Statements are
equivalent to the same procedures with a wait
statement, whose sensitivity clause includes the
signals mentioned in the parameter list.

• The equivalent procedure

• A concurrent procedure call

• call_proc p ( s1, s2, val )

• call_proc process is
• begin
• p ( s1, s2, val )
• wait on s1, s2
• end process call_proc

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Subprograms procedures
Function encapsulates a collection of
statements that compute a result Þ generate an
expression Procedure encapsulates a
collection of sequential statements to execute Þ
generate a statement
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GenericsConfigurations
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Generics

• Can we write general models instead of making
  specific models with VHDL ?

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Generics

• Motivation
• Oftentimes we want to be able to specify a
  property separately for each instance of a
  component.
• VHDL allows models to be parameterized with
  generics.
• Allows one to make general models instead of
  making specific models for many different
  configurations of inputs, outputs, and timing
  information.
• Information passed into a design description from
  its environment.

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Generics

• A generic

AND gate
entity AND_GATE is generic ( N natural 2
) port ( A in bit_vector (1 to N )
Z out bit) end AND_GATE
architecture generic_ex of AND_GATE is begin
process (A) variable AND_OUTbit
begin AND_OUT 1 for k in 1 to
N loop AND_OUT AND_OUT and A(k)
exit when AND_OUT 0 end
loop ZltAND_OUT end process end
GENERIC_EX
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Generics

• A generic declares a constant object of mode in
  (read only) The value of this constant can be
  specified as a static expression globally
• Then it can be used in the entity declaration and
  its corresponding architecture bodies.
• The value of a generic must be determined at
  elaboration time (explicitly specified at least
  once).

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Generics

• The value for a generic may be specified
• in an entity declaration
• in a component declaration
• in a component instantiation.

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Generics
entity ANOTHER_GEN_EX is end archiecture
GEN_IN_COMP of ANOTHER_GEN_EX is component
NAND_GATE generic (M INTEGER) port
(A in bit_vector(M downto 1) z out bit)
end component component AND_GATE
generic (N natuaral 5) port (A in
bit_vector(1 to N) Z out bit) end
component signal S1, S2, S3, S4 bit
signal SA bit_vector( 1to 5) signal SB
bit_vector( 2 downto 1) signal SC
bit_vector(1 to 10) signal SD bit_vector(5
downto 0) begin N1 NAND_GATE generic map (6)
port map (SD, S1) --N2 NAND_GATE port map
(SB, S2) A1 AND_GATE generic map (N gt 10)
port map (SC, S3) A2 AND_GATE port map (SA,
S4) end GEN_IN_COMP
component declarations
component instantiations
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Generics

• Notes
• Generic information is static
• ------it can not be changed during the
  simulation.
• Generic value is instance-specific
• ------different instances of the same component
  can have different values.

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Configurations

• Why we need configurations ?

It may be convenient to specify multiple views
for a single entity and use any one of them for
simulation. For example, there are three
architecture bodies, called FA_BEH, FA_STR, and
FA_MIXED, corresponding to an entity FULL_ADDER.
We can select any of them for simulation by
specifying an appropriate configuration.
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Configurations

• Configurations
• A VHDL description may consist of many design
  entities, each with several architectures, and
  organized into a design hierarchy. The
  configuration does the job of specifying the
  exact set of entities and architectures to use,
  in other words, binding component instances to
  entities.

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Configurations

• Configurations
• Specify which architectures to use for a
  particular component
• Specify which parameter values to use for a
  particular component

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Configurations

• A configuration is therefore used to bind the
  following pairs
• An architecture body to its entity declaration
• A component with an entity
• Definition
• Associating an architectural description with a
  component in a structural model.

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Configurations

• Choose component

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Configurations

• VHDL provides two ways of binding
• By using a configuration specifications
• Is used to bind component instantiations to
  specific entities stored in design libraries.
• By using a configuration declarations
• The binding can be performed after the
  architecture body has been written.
• More than one configuration declaration for an
  entity is possible.
• The power lies in that the sub-components in an
  entire hierarchy of a design can be bound using a
  single configuration declaration.

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Configurations
Configuration specifications
------A VHDL construct which helps associate a
particular architecture with an instantiated
component
component MYCOMP port ( .) end component
for U1 MYCOMP use entity work.MYCOMP(BEHAV)
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Configurations
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Configurations
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Topics

• Aliases
• Subprograms
• Generics Configurations