A PCB technology

1
Product Engineering
A PCB technology for each of your application
P. Privé June - 04

2
Glance on production

• More than 50 of PCB class 7 and more (L/S lt
  120µm) are 10 12 layers PCB
• 90 of these PCB are 1.6mm thick ? Layers
  thickness lt 150µm (4 5 mils)
• Aspect ratio for 1.6mm thick board around 5
  (Min diameter 0.3mm) 60 of population 10 of
  production around 2 to 2.4mm with AR 8
• Less than 10 of 1.6mm thick PCB with 0.25mm hole
  diameter
• 2.4 mm thick PCB, min hole 0.3mm
• The only PCB with Aspect ratio around 10 are
  4.5mm and more thick PCB ? Press fit holes

3
What is High Performance ?
Each designer or each EOM has his own
definition, but several items could take in
consideration for "High Performance" PWB's  
1.) Boards with special thermal requirements
? they will operate continuously or
intermittently in high temperature
environments ? they will have a high
concentrations of power in small areas 2.)
Large or high layer count multilayers ?
base material elongation specially with thin
core ? boards with complex etched patterns
requiring precise registration
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What is High Performance ?
3.) Boards requiring Controlled Thermal
Expansion characteristics for SMT technology 4.)
Boards with special or tightened electrical
requirements controlled impedance
characteristics High signal speed 2 GHz or
more 5.) Boards which will operate at microwave
frequencies and therefore require materials with
low loss or low dielectric constant   6.)
Boards which require high density interconnection
(HDI) Microvia technology 1N1 to 2NBVH2
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Thermal expansion

• Fine pitch Smt component, BGA, µBGA required
  Accurate position Thermal stability during
  assembly and process
• Solutions
• ? Specific base material Aramid CuInCu
  Specific product reserved for niche product
  Polyimide or recent BT resin High tg
  material are not always sufficent Low CTE
  material (tg 150 or 170 C)
• ? Co design
• Choose build up with low resin content glass
  type adapted Copper balance Ground or
  Power layers under external layers Avoid non
  symetric Cu thickness on thin inner layer

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Tightened electrical requirement

• Controlled impedance characteristics require
  good thickness control on dielectrics and
  thighten tolerances on line width
• High voltage more and more used in PCB
• Solution ? Co design Avoid high
  thickness on ppg dielectrics ( high amount)
  Avoid High resin content in ppg Good copper
  balance, in particular on high Cu thickness
• ? Use CAF resistant material mainly for small
  space between holes ( PCB at high voltage)
• ? Dielectric constant of a glass/resin composite
  is proportional to the volume ratio of glass to
  resin selection of laminate constructions and
  prepreg styles is a necessity

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High Speed/Low Loss MaterialsDk vs. Df
Improved Speed Signal Integrity Region
5.0
High Tg Epoxy
Polyimide
N4000.7 SI
N4000-13 Low Loss Epoxy
Std. Epoxy
4.0
N6000
Dk _at_ 1MHz
BT
N6000 SI
Epoxy Thermount
N4000-13SI
3.0
SI
Teflon/Glass

2.0
.005 .010 .015 .020 .025
Df _at_ 1 MHz
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HDI Material comparison
Property RCC E-glass
LD prepreg prepreg Z
axis range 5 1.7 - 4.5 1.7 -
4.5 X-Y CTE range( ppm / C ) 30 -
40 10 - 16 10 - 16 Tg range C
130 - 170 130 - 250 130 -
250 Maximum 80µm 240µm
240µm laser drillable 2, 3 plies constr.
2, 3 plies constr dielectric thickness Outer
dielectric 15 10
10 Tolerance

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Product mix
Product mix
2 drivers ? technological diversity ?
High tech products
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ELVIA PCB PRODUCT FAMILIES
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PCB Solutions
Halogen free
CuInCu
Lead free assembly
Back Panel
Planar
Material
Metal Core
Metallic Finishes
Thermal Dissipation
PCB on carrier
Mature Technology
Flex Rigid
SMI Pcb
Multilevel Flex rigid
HDI Pcb
High Frequency
µVIA
Sequentiel Buil up
Filled µvia
PTFE PTFE on Sole
Stacked µvia
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Controlled impedance

Typical tolerances  /- 10 Limited
series  /-7 Software modelisation
Definition of build-up and line width (Etch
compensation) Zc measurement single and coupled
lines (reflectometer)
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Back Panel Assembly
Larger Conventional  700 x 500 mm Large
Size  950 x 600 mm Application Alcatel
ADSL 4.5 mm thick , 20 layers Mini Dry Press
Fit Thru hole
Thicker Thickness to 4.5 mm in standardto
6.5 mm in adapted flow chartto 8mm in progress
More than 26 layers Application   Alcatel
Transmission Mini Dry Press Fit Thru hole
Metallic finishes  Reflowed Tin-Lead Hot Air
Levelling E NIG Immersion TinImmersion Silver

Controlled impedance
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Planar
Pcb replace conventional wired components with
- Smallest size - High heat dissipation
- Electro Magnetical compatibility - High
component integration - High reliability
Characteristics  - High count of layers  8
to 24 - Thin laminates  0.1 to 0.2mm -
High copper thickness  70 to 210 µm
- Plating edges  ½ plating holes
Application - Automotive (Epcos, Microspire)
TelecomAlcatel Converters)
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Metal Core
10 Layers Copper core thickness 400 µm
800 µm Sequential build-up Buried via holes
Controlled impedances Metallic finishing 
Hot Air Levelling Application  Heat dissipation
An adapted process to guarantee the reliability
of holes through the opening in core
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Thermal requirement

• New component with high thermal dissipation,
  Close environement with few air circulation, Hard
  environmental conditions (Avionics, ...)? The
  PCB must operate continuously or intermittently
  in high temperature environments ? Resin and
  copper are facing oxytation The resin turn
  brown The copper surface treatment could be
  distroy Our Solutions ? Increase the thermal
  dissipation on PCB Metal core , ? or Metallic
  carrier glued on PCB Blind or holes under
  component, Thermal layers Thick copper . ?
  New kind of material (MOT gt 130C) IS410,
  N4000.11 ? Co design to increase the
  reliability Avoid isolated copper area,
  Prefer Pads on external layers ? Avoid high
  resin content Prefer mineral filler in Blind
  hole (N4000.7, ...)

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PCB on Carrier
4 layers PCB NiAu bond On aluminium carrier
with No Flow Prepregs
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SBU
Sequential Lamination  2 lamination steps, 3
drilling levels Via in pads with multilevel
connection Layers  14 Base materials high
Tg 170C or Low CTE Metallic finishing 
Chemical NiAu
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µvias technology
A specific process Large Windows Some
Parameters
Reliability µvia in Pads
Design to manufacture A Cost effective
solution An industrial solution Burried
µvias
A solution which increase the density of your
design 1N1 1N(BVH)1 µvia and
SBU 2N2 µvia small size
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Microvias
High Density  Micro BGA - CSP Via in Pads
Requires MicroVia Holes
This process could be applied on  - All kind of
glass reinforced materials (FR4, High TG, High
frequency, Low CTE ) Preferred
solution  Glass reinforced materialsCopper cap
technology
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Microvias
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Cost comparison
14 pth
1101
282
28bvh2
110bvh1
66
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Microvias design solutions
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Build up to increase density
Sequential Buld Up and µvia
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Microvias 2n2
Industrial solutions available 2n(BVH)2
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Microvias 2n2
Industrial solutions available 2n(BVH)2
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Microvia Board

• High density interconnection pcb

• 18 layers, 116BVH1
• Thickness 2.4 mm
• PTH (Diam 0.25 mm)
• Buried via holes (1-17) Diam 0.25mm
• µvias holes (ES/2-SS/17)
• µvia material RCC
• metallic finish Ag
• Customer Alcatel USA

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Thermal Stress Tests

• Dip test in SnPb 3 x 10 s _at_ 288C

• High Tg Material

• N4000.7

• No Plating cracks
• Resin Cracks in bvh
• Cracks in base material
• Voids or resin recession

• No plating cracks
• No resin cracks in bvh
• No cracks in base material
• No resin voids

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28BVH2 µvia Reliability

• 500 thermal shocks -55125C

• Bvh holes copper cracks, some in High Tg and
  very few in 4000.7 Cu thick gt20µm

No Craks in 2 levels µviasOnly in BVH 2 levels
µvias is a reliable way to manufacture HDI
PCB Base Material with mineral filler ( N4000.7)
Better Reliability

• Pth holes no copper cracks, inner layer
  junctions ok

• µvias no cracks, junctions Ok

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µvia in Pads
µvia in Pads is Possible
BGA Component
SMT Component
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µvia in Pads

• Xray Inspection according IPC A 610

Xray inspection on soldered BGA - Overview
X ray inspection on soldered BGA- detail with
acceptable bubbles
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HDI Board
Base Materials  High Tg 170C High layers
count  26 Large Size  560 x 320 mm High
Aspect ratio  10 1 (0.3mm drilled holes / 3mm
thick board) Micro vias  2 sides of laser Via
holes(100µDiam/100µ Thick) High I/O count 
1300I/O per BGA Density 100µm line width
space

• Controlled impedances 20 Levels of
  Zc(microstrip, stripline, differential
  stripline)
• Buried capacitance 2 levels of BC2000 (high
  pot test on inner layer finish product)
• Plug via holes
• Metallic Finishing 
• Hot Air Levelling

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Large size and high count of layers board
JDVPM Alcatel CIT 508x325 mm16layers (1141
)96 BGA 0.7mm pitch Line Space 100µmHole
diam 0.3mmQty PTH 26568µvia 120µmQty µvia
27346
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HDI and Test
Fixture with 40000 pins of 0.3mm
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HDI and Test

• Electrical test
• flying probes EquipmentsTechnical
  Capabilities   maximun board size 850 x 700
  mm pitch down to 0.3 mm
• 4 double side universal testers Technical
  Capabilities   
• test field size 487 x 325 mm
• test field grid double density
• Adaptation of fixtures to face high I/O of
  microBGA and CSP
• pitch 1mm up to 34 x 34 pads
• pitch 0.5mm up to 20 x 20 pads

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HDI PCB and Test
Fixture PCB side
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HDI PCB and Test
Fixture Grid side
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Large size, High count

• Thin layers (lt 5mils) and large size PCb (gt300mm)
  need an accurate control of base material
  elongation
• Solutions
• ? Our experience on such PCB analysis of
  elongation Adjustment at each design ?
  Specific solution to insure a full electrical
  test
• ? Base Material specific base material (
  N4000.7,...)with mineral filler resistant to
  several thermal cycling and good dimensionnal
  stability ? Co Design Copper balance
  adjustment on inner external layers symetrical
  build up Increase the Difference between
  Hole and Pads ? Pads diameter ( not allways
  possible) ? hole diameter till 0.3mm (Aspect
  ratio to 10)

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HDI board

• Boards which require high density
  interconnection (HDI) microvia technology
  (1N1) Blind via technology (2nBVH2) or
  sequential buildup
• Solutions ? High level of experience in
  Industrial PCB with µvia Large Windows and
  CO2 laser
• ? Co design to answer your problem at the
  lowest cost Specific base material to support
  several lamination (Low CTE material) Reinforced
  material prefer instead of RCC Used of µvia
  technology to each density board µvia on
  BVH Several layers of µvia µvia and
  SBU Burried µvia ? Prefer glass reinforced
  base material (PPG instead of RCC)? Copper
  thickness 9 µm on external layer and on Cu
  reinforced layers

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µvia thin board
Customer ACUNA 65x47mm8layers
16bvh10.8mm thickNiAu finishes/ Au
electrolytic edge connectorsµvia 110µm
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Burried via holes Inner layers
Our solution to replace thin Bvh inner layer
First lamination2 cores Layers 2-7 Layers
9-15
Second laminationCore1 innerlayer core 2
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Burried via holes Inner layers
Lower Cost Replacing 4 BVH inner layers 3
outer layer processes with µvia solution instead
of 5
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Via Fill
First Drivers for Via fill From a long time in
Chip substrate without no PTH Cheapest solution
to get very dense PCB without any PTH Main use
PCb for handy - far east facilities In
high degree of miniaturisation Via in Pads,
Stacked µvia
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Via Fill
Process - Conductive Past Lower
conductivity than copper Air inclusion - Cu
Plating Conductivity Thermal conductivity
could not be an additive process Development
program Collaboration with Thales and Atotech
Cu plating process To be checked µvia and PTH
on the same board ? Chemistry to use
Adequation with asseembly process Via in
Pads Stacked µvia A soultion to earn space /
staggered µvia
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Via Fill
Dimple Effect
µvia get with Dc pattern plating
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High Frequency
Base Material Rogers RO 4000 Low DK / Low DF
Material Cyanate Ester Epoxy HF on glass E
or SI Build Up Full Hf material Mixt Build Up
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High Frequency

• Boards operate at high frequencies, manage
  high volume digital data.
• Solution ? Low Loss or Low Dk material Base
  material as RO 4003, High frequency Epoxy (
  N4000.13) Base material with Si reinforcement
  ? Mixt build up Low Er on FR4 base material ?
  Burried Capacitance Decoupling Plane ZBC or
  alternative ? Keep lowest density with lowest dk
  or df Same Zc with larger line on high frequency
  epoxy than on FR4(High frequency FR4
  N4000.7SI-cost x2 fr4- or N4000.13- cost x3 FR4)

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High Frequency - Sole

• Materials
• Roger 4003
• Finishes
• NiAu ( 0.1µMau)

High Frequency substrate and alumina bond on
metallic carriers with silver reinforced
glue-Specific pattented process
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PTFE PTFE on Sole

• Development in 2004 - 2nd Half PTFE RO 6000
  or Neltec base material PTFE on Sole ( Brass)

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Flex Rigid

• Build Up 4 to 18 layer Flex rigid (Double or
  single side flex) Sequentiel build up
  Lamination parameters adapted to each
  material FR4 High Tg Low CTE
  Polyimide Kapton ( Adhesive less) layer as
  internal or external layers
• Flex protection Coverlay Flex Solder

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Flex Rigid

• Ecobond Protection Protection of interface by
  epoxy glue

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Flex Rigid

• Some Parameters Base Material No flow PPg
  Htg Arlon Flex Adhesive less 50 µm dielectric
  thick Panel size 610x460 mm
  Multipanel production on standard pcb
  line Design rules Differnce hole and Pads
  350 µm mini Line space and width on flex part
  120µm Non functionnal line on the edge of
  flex Cross hatching on the other side of
  flex Non functionnal pads on flexible layers
  Rivet Coverlay Bikini method Economic

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Multilevel Flex Rigid

• 2 kind of Multilevel Flex rigid in progress

Rigid part
No Flow PPG
Flex IL
Epoxy Glue Film
Flex IL
No Flow PPG
Rigid part
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Base Material
REQUIREMENTS FOR MULTILAYER MATERIALS
BT N5000 POLYIMIDE N7000
N4000-6 PCL-FR-370
HIGH Tg
N4000-7 N4000-11
LOW CTE
HALOGEN FREE MATERIAL
PCL-HF-541
ANTI CAF MATERIAL
N4000-13 N8000 RO4350B
LOW Df
N4000-13 RO4003
LOW Dk
GREEN MATERIAL
THERMAL RESISTANCE
HIGH FREQUENCY
HIGH SPEED
NEEDS IN PWB DEVELOPMENT
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Metallic Finishes
A wide range of solution in house adapted to
Assembly process Component Technology ? Hot
air Levelling ? Electroless Nickel Immersion
Gold ( ENIG)- Atoteh selective NiAu Wire
bonding finishing a long experience Over 50
of our production Total NiAu PTh covered or
plugged with Solder resist ? Chemical Silver
Alpha Fry ? Electroless Tin Atotech Qualificat
ion with Thales Group Total or selective
Electroless Tin / PTH with solder resist In
Development ? Lead free HASL
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Lead Free assembly and Halogen free
Halogen free material ? Regulation RoHs
a Limit on PBB and PBDE ( Bromide components)
content Till today the majority of base
material ( FR4, Low CTE , High Tg,..) do not
content any of these components ? Halogen
free material bromide replace by
phosphorous component Advantage higher
degradation temperature than FR4
Lead Free Assembly ? Higher temperature than
with lead 260C during 4-6sec several time
( 2xIR Wave, repair) Degradation of resin
(turn brown-oxydation) High stress on PCB
High aspec ratio / BVH ? Collaboration with
several assembly shop (Alcatel, Thales, Altrel,
...) Solution to be confirmed High MOT
or low CTE base material Metallic finishes
influence
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Elvia - PCB COUTANCES TECHNOLOGICAL ROAD MAP
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Technology Road Map - chart 1
Materials
In Development
Industrial phase
PTFE
Qualified
Thermount
Halogen Free
Test done
Epoxy HFN4000.13
Buried Components
Alternative Mat Buried Capacities
High Er
Finishes
Discret Embeded Capacities
Chemical Tin
In House
OSP
lt 2003
2003
2004
2005
59
Technology Road Map - chart 2Janvier 2003
High Density
µvia 4n4
In Development
Industrial phase
Embeded µvia
Qualified
Test done
Filled µvia
Interconnection
Flex Rigidn4 flx
Flex Rigidn2flx
BP 5mm tck
BP gt5mm tck
BP 950x500mm
BP gt7.5mm tck
HF substrate on sole
Optical Connection
lt 2003
2003
2004
2005
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PCB BP ROAD MAP
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PCB Road Map
Parameter 2003 2004 2005
Technology
2nBVH2Flex RigidSBUBVH inner LayerZ axis drilling milling Embeded µViaStacked µvia3nBVH3Multilevel Flex RigidEmbeded Capacitance Embeded Resistors Filled µvia
Substrate
Materials Fr4High TgPolyimideLow CTEHalogen FreeRo 43xxMixt build up HFFR4 Fr4High TgPolyimideLow CTEHalogen Free Ro 43xx Mixt build up HFFR4 High Tg Low CTEHigh speed MaterialAnti Caf Fr4High TgPolyimideLow CTEHalogen Free Ro 43xxMixt Build up High Tg Low CTEHigh speed MaterialAnti CafPTFE or Equivalent
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PCB Road Map
Parameter 2003 2004 2005
Interconnection
PTH Via/Pad Diam. 0.25/0.56mm 0.25/0.50mm 0.25/0.45mm
Aspect Ratio 10/1 12/1 12/1
µVia Hole /pad diam. 0.13/0.35mm 0.1/0.3mm 0.08/0.25mm
µVia Aspect Ratio 0.8/1 0.8/1 1/1
Technology Large Window Large WindowStacked µvia Large WindowFilled µviaDirect Drilling ( 5µCu)
Tracking
Inner Line/Space 75/100µm 75/100 µm 75/75µm
Outer line Space 100/100µm 75/100µm 75/100µm
Inner Cu Thick. 105 17µm 240-17µm 240-12µm
Outer Cu Thick. 70-9µm 70-5µm 105-5µm
Impedance 50/100? 10 50/100? 7 50/100? 5
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PCB Road Map
Parameter 2003 2004 2005
Build Up Substrate
Min Dielectric thick 50µm 25µm (Flexible) 25µm
Nb of Layer 30 gt30 gt30
X/Y dimension 4005605301000 (BP) 5005606001000(BP) 5005606001000(BP)
Thickness 0.8 / 3.5mm5mm(BP) 0.6/3.5mm8mm(BP) 0.6/3.5mm10mm(BP)
Solder resist
Material Probimer 77Tayo PSR 4000Kapton Protection Probimer 77TAYO PSR4000 Kapton Protection Peter Flexible Probimer 77TAYO PSR4000 Kapton Protection Peter Flexible
Thermal InkPlugged Via Photoimageamable Marking Photoimageamable Marking
Accuracy /-50µm /-50µm /-50µm
64
PCB Road Map
Parameter 2003 2004 2005
Metallic Finishes
Fused SnPbHASLChemical AgENIGChemical Sn Fused SnPbHASLChemical AgENIGChemical SnOSPMixt Finishing Lead Free HASL alloy Chemical AgENIGChemical SnOSP Mixt Finishing
By subcontracting