Chap' 5: State Machine Design

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Chap. 5 State Machine Design

• Chapter Design Objectives
• Manual state machine design
• How to design state machines for complex
  synchronous sequential digital logic circuits
• Automatic state machine design
• How to convert algorithmic descriptions into HDL
  code that can be synthesized into working
  circuits
• The general form of the circuit that will be
  synthesized from an algorithmic HDL description

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State Machine Design

• Used for systematic design of synchronous
  sequential digital logic circuits
• Modification of FSM Method
• FSM (Finite State Machine) method insufficient
• FSM method only suitable for small sequential
  circuits with small numbers of external inputs
• Allow more complicated checks for state
  transitions
• Uses RTL statements within the states
• Within one state, all RTL statements execute
  concurrently
• Permits systematic conversion from algorithms to
  H/W
• Variation of State Machine Method
• Algorithmic State Machine (ASM) Method
• Uses a graphical notation referred to as an ASM
  chart

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Algorithms

• Formal definition of an algorithm
• A general step-by-step procedure for solving a
  problem that is CORRECT and TERMINATES.
• A proof is required before a procedure can be
  called an algorithm.
• Informal definition of an algorithm
• A computer-program-like procedure for solving the
  problem given.
• Algorithm description methods
• Old (outdated) method flowchart
• Pseudocode free-form procedural description

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Structure of General Digital Circuit
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Partitioning of Digital Circuits

• Control Logic Section
• logic required to generate control signals for
  registers, adders, counters, etc.
• Datapath Section
• all logic not included in the control logic
  section
• registers, adders, counters, multiplexers, etc.
• typically the word-sized data manipulation and
  storage components through which the data flows

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Example Layout for a Chip
input data
control and status signals
output data
datapath elements
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Manual State Machine Method

• (1) Pseudocode
• create an algorithm to describe desired circuit
  operation
• (2) RTL Program
• convert the pseudocode into an RTL Program (HDL
  or ASM chart format)
• (3) Datapath
• design the datapath based on the RTL Program
• (4) State Diagram
• based on the RTL Program and datapath
• (5) Control Logic Design

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RTL Program

• HDL Format
• Like a pseudocode description, except that each
  step is one state of the state machine
• All operations within one state execute
  concurrently
• All operations are RTL operations
• ASM Chart Format
• Uses a graphical notation that resembles a
  flowchart
• Main difference
• All operations within one state execute
  concurrently

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ASM Charts

• Consists of 3 types of constructs
• State object
• Condition object
• Conditional output object

Example ASM Chart
How could we replace this with a conditional
output object? Is there any difference in
operation?
RTL Statements
condition
RTL statements
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Manual State Machine Design Example Coin Changer
Circuit

• Problem Design a coin changer circuit that
  changes 1000 Won notes to 100 Won coins.
• Example usage
• the coin changers used in electronic game arcades.

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Step 1 Pseudocode

• (1) Initialize COIN_OUT to 0
• while (TRUE) do
• (2) REJECT ? 0
• (3) Wait until MONEY_INPUT
• (4) If (not MONEY_VALID) then
• REJECT ? 1
• Go to Step (2)
• (5) For i 0 to 9 do
• COIN_OUT ? 1
• COIN_OUT ? 0
• endwhile

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Step 2 RTL Program (HDL Format)

• (0) COIN_OUT ? 0
• while (TRUE) do
• (1) REJECT ? 0If (MONEY_INPUT 0) then
• go to Step (1)
• else if (MONEY_VALID 0) then
• (2) REJECT ? 1else
• (3) COUNT ? 0
• (4) COIN_OUT ? 1
• COUNT ? COUNT 1 (5) COIN_OUT ?
  0 if (COUNT lt 9) then / concurrent
  with above statement /
• go to Step (6)
• endwhile

Each step corresponds to a state in the
control logic. The RTL operations within a
single state are executed concurrently.
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Step 2 RTL Program (ASM Chart)
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Step 3 Datapath
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Step 4 State Diagram
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Step 5 Control Logic
Example of one-hot control logic design method
(refer to pp. 18-19 of this ppt file)
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Control Logic Design Methods

• One-FF-per-state method
• also referred to as one-hot or delay element
  method
• uses one FF for each state of the state machine
• PLD-based method
• uses encoded states
• number of FFs used integer_part (log
  (number_of_states))
• results in the most compact implementation
• Sequence-counter method
• for use with cyclical state transition patterns
• e.g., a CPU with equal numbers of states for each
  instruction
• outputs of the counter are the control logic
  states

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One-FF-Per-State Method

• Uses one-to-one transformations from state
  diagram to digital logic components
• Also applicable to ASM charts
• Transformations
• state in state diagram
• transforms to a D flip-flop
• transition from one state to another in state
  diagram
• transforms to a path from the Q or Q output of
  one state flip-flop to the D input another D
  flip-flop
• labeled transition in state diagram
• AND gate with the labeled condition
• labeled (conditional) signal activation also
  leads to AND gate
• Several transitions into a single state
• OR gate with one input for each transition

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One-Hot Transformation Example
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PLD-Based Control Logic Example
Next State Variables
Current State Variables
control signal outputs
conditions (status signals)
Contains programmed logicto implement next
stateand output logic equations
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PLD-Based Implementation (Using an EPROM as a
PLD)
A14
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A14
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Overall Manual State Machine Design Approach

• Write down a pseudocode solution
• test it out using a short computer program
• Convert the pseudocode to an RTL program
• try to optimize ASM chart, so it uses a small
  number of states
• can use HDL format or ASM chart format
• Derive the datapath from the RTL program
• figure out the datapath components and signals
  needed
• Form a state diagram with states and control
  signal activations
• Derive the control logic design
• one-hot or PLD-based approach

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Automatic State Machine Design

• Describe the desired circuit using pseudocode
• Convert the pseudocode into an HDL program
• If the pseudocode is converted into an ASM chart,
  then a conversion tool (e.g., the Exsedia Nimbus
  tool) can be used to automatically convert an ASM
  chart into synthesizable Verilog or VHDL code.
• Use a synthesis tool to convert the HDL code into
  a working hardware circuit
• Implement for the target hardware architecture

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Recommended Pseudocode Format

• (0) initialize variableswhile (true) do (1)
  first step of algorithm (2) second step of
  algorithm . . . (k) for (i 0 i lt max
  i) . . . (m) function call (n) nth
  step of algorithmendwhile

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Corresponding Synthesizable Verilog Code

• always _at_(negedge reset_n or posedge clk) begin
  if (reset_n) begin state lt 0 (other
  initialization operations) end else begin //
  on posedge clk state lt state 1 //
  auto-increment state case (state) begin
  0 begin // first step of
  algorithm end 1 //
  second step of algorithm 2 begin
  ret_state lt 3
  state lt FUNCTION_1 end
  3 FUNCTION_1 // 1st step of
  function
  FUNCTION_1k state lt ret_state // return
  from function default
  display(Unknown state) endcase end
  // of else (posedge clk)end // of always

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Conversion of For Loops

• Conversion of for (i 0 i lt max i)
  endfor
• Options
• Use same sequence of operations
• i 0
• while (i lt max) i i 1 . . . Endwhile
• Decrement the count instead of incrementing I
• count max
• repeat count count 1 . . .until
  (count 0)
• Other equivalent series of operations also
  possible

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Use of Code Templates

• Use the code in pp. 178-179 as a template for the
  creation of new Verilog programs
• Typical pseudocode operations used and
  corresponding HDL code
• Table 5.2 (p. 178)
• For loops discussed on previous page

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Textbook Examples

• Manual state machine design
• Factorial circuit
• Vending machine
• Automatic (synthesis-based) state machine design
• Vending machine
• Correspondence to manual solution shown
• LCD controller

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Example Two-Phase Handshake Transmitter Circuit

• Used to communicate between two circuits in
  different clock domains (i.e., clocked by
  different clock signals)
• In large or high-performance circuits, different
  circuits (or subcircuits) will use different
  clock inputs because of clock synchronization
  difficulties or simply because they are
  independent circuits
• Communication of data packets between such
  circuits requires a handshaking protocol
• Solution implemented using the automatic
  synthesis-based method instead of the manual
  state machine design method used in Example 5.2

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Pseudocode

• 1. req ? 0
• while (TRUE) do
• 2. wait until (ready 1) // data ready
• 3. data ? data_to_be_sent
• 4. req ? not req // invert req value
• 5. wait until (ack req)
• end while

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Synthesizable Verilog Code

• always _at_(negedge reset_n or posedge clk) begin
  if (reset_n) begin req lt 0 state
  lt 0 // state should be a 2-bit reg
  signal end else begin // on
  posedge clk state lt state 1 //
  auto-increment current state case (state)
  begin 0 if (ready)
  state lt 0 // repeat until ready 1
  data lt data_in // assume data_in is data to be
  sent 2 req lt req // send
  request signal 3 if (ack ! req)
  state lt 2 // stay in this
  state until (ack req) default
  display(Error Unknown state) endcase
  end // of else (posedge clk)end // of always