OPTIMIZATION OF CURRENT MODE MULTIVALUED LOGIC CIRCUITS

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OPTIMIZATION OF CURRENT MODE MULTIVALUED LOGIC
CIRCUITS

• Avni MORGÜL and Fatma SARICA
• Bogaziçi University
• ElectricalElectronics Engineering Department
• Istanbul, TURKEY
• Presented By Avni Morgül

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MVL Multi-Valued Logicfills the gap between
digitalanalog

• More than two logic level (rgt2)
• Logic functions may be implemented
• Using less number of transistor (smaller chip
  area)
• Using less number of interconnections
• Faster
• Disadvantages
• Static power dissipation
• Lower noise margin
• Applications
• Faster signal processor circuits with reduced
  chip area and less interconnections.

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Definitions
Number of discrete values radix (r )
discreteout
l
In the current mode implementation each logic
level is represented by a current level Ij j?Ib
, The base current Ib corresponds to one step of
discrete current variation. A logic level l
corresponds to an interval of cont. variable, y y
? l y(j-0.5)Ib ? y lt (j0.5)Ib
Ij
Ib
y ?
(j0.5)Ib
(j-0.5)Ib
jIb
continuous input
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ImplementationBy using current-mode CMOS
circuiti. The basic circuit Elements
the symbol
the circuit
n-type current mirror
Multiplying and re-directing a current
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Inverter
z
6
min(x,y) gate
min(x,y) x? y x y
y
11
11
P
N
y
y
y
x
x
N
N
z
11
11
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Threshold circuit
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Comparison with binary FA
3-bit binary-RCA (84 trans.) 160µm85µm
MVL- radix-8 adder (12 trans.) 87µm24µm
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Level Variation Problem

• The level of the gate output signals may vary
  from the predefined discrete levels due to
• The non-idealities in the circuit (Mismatch)
• Variation of input signals
• Noise

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Statistical Mismatch Analysis

• Mismatch models of MOS transistors include two
  terms
• a size dependent and
• a distance dependent term
• In this study we will concentrate on size
  dependent term and we assume that variations in
  W/L ratios will be the dominating term
• The drain current may be expressed as follows

where
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Statistical Mismatch Analysis

• The variance in z Iout due to the dimension
  mismatches in the transistors may be defined as

Calculated output current deviation
Simulated output current deviation
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LEVEL RESTORATION

• Unlike CMOS binary logic circuits, CMOS MVL
  circuits are not self restored.
• This causes noise margin to be critical after a
  number of stages.
• A level restorer circuit must be used after a
  certain number of stages to recover the signal

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Level Restoration

• The maximum number of identical structures that
  can be cascaded, without loosing a predefined
  logic level at the output, is limited.
• Maximum radix of a given MVL implementation
  depends on logic level degradations of basic
  gates, such as min gate, ?min.
• The allowable logic level degradation or a
  standard deviation for each m-input gate with
  radix r can be determined by

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Level Restoration

• It is necessary to restore the deviated levels
  after a certain number of cascaded gates

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Statistical Analysis
Deviation of the output current from the nominal
value, for k cascaded stages
60
z, ?A
40
y 30 ?A
20
0
20
40
60
80
x, ?A
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8-Level Restorer Circuit
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Simulations
variation
Simulation result (100 runs) for 6 stages of min
circuits with large transistors
Worst case of 100 Monte Carlo simulations for 3
cascaded stages of min circuits with small
transistors
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Simulations

• Spice simulations indicate that maximum allowable
  number of cascaded min circuits using the
  dimensions of W/L40/20µm, is 6
• The output deviation reaches the critical noise
  margin (1/2 I0) after the 6th stage for large
  transistors, and it is not possible to add one
  more stage
• The max. number of stages for small transistors
  (W/L20/10µm) is only 3.
• A restorer circuit is necessary after these three
  stages. Restoration circuit corrects the
  deviations at the output current.

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COMPARISON

• Qestion Which one of the following situations
  is advantageous in the area consumption and noise
  margin point of view
• using a restorer circuit or,
• increasing the dimensions of the active
  elements?
• The min circuit is selected as a model circuit.
  Dimensions of the model circuit are chosen such
  that the output current of the specified number
  of the cascaded blocks remain within the critical
  noise margin.
• Same circuit is built by using minimum size
  transistors, and a restoration circuit. Total
  areas are calculated for both circuit and
  compared.

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COMPARISON

• Layouts of the two circuits are drawn using the
  Magic Layout program and total areas of the
  circuits are calculated. It is found that using a
  level restoration circuit reduces the total area
  consumption nearly 25, compared to large sized
  transistors.

Six stages with W/L20/10µm, plus the restorer
circuit. Total area439µm226µm
Six stages with W/L40/20µm, Total
area497µm271µm
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CONCLUSION

• The number of cascaded stages is limited in the
  MVL implementation due to the mismatches and
  smaller noise margins compared to binary logic.
• The number of cascaded stages may be increased
  either by increasing the sizes of transistors or
  by adding a restorer circuit after a certain
  number of stages.
• We compare these two solutions and found that the
  solution with a restoration circuit saves about
  25 in the total chip area.