Todays Subject

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Todays Subject

• Continue on some basics on single-wall
  CNT----chiral length, angle and band gap
• Other properties of CNT
• Device applications
• Growth of CNT
• Si nanowires
• Other nanowires
• Growth Challenges.

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Roll Carbon Nanotube from Graphene
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Ch n a1 m a2 ?(n, m) (n, m are integers 0 ?
m ? n).
cos? Ch ? a1 / Cha1.
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Nanotube Chirality
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4
Examples of Band Structures
One-dimensional energy dispersion relations for
(a) armchair (5, 5), (b) zigzag (9, 0), and (c)
zigzag (10, 0) carbon nanotubes.
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Bandgap of Semiconducting Tube
5
6
ATM or STM Used to Determine Chirality
(11,7)
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Multi Wall Tubes
Multi-wall CNT
TEM Image
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Material Properties of CNT-continued
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Comparison of Other Materials to CNT
Space Elevator
CNT cable Super strong, light weight
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Material Properties of CNT-continued
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Electronic Applications
CNT transistor
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Demonstration of CNT Memory Design
http//www.nantero.com/index.html

• Applied charge make CNT ribbons bend down to
  touch the substrate or bend up back to its
  original state.
• Ribbon-up gives 'zero' and ribbon-down is 'one'.

13
Structure

• Fabricated on a silicon wafer, CNT ribbons are
  suspended 100 nanometers above a carbon substrate
  layer.

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Off-State
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On-State
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Read-Out
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Structural and Mechanical Applications
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CNT interconnect Lines
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Bottom-up Approach for CNT interconnects
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Sensors, NEMS Applications
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CNT-based Bio Sensors
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(No Transcript)
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Carbon Nanotube Growth
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Three Basic CNT Growth Methods
C
A
B
A Laser ablation B Arc discharge C Catalytic
chemical vapor deposition (CCVD). All currently
known methods consist of some variant of one of
these approaches.
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Bottom-up Growth of CNTs
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CNT Nanoelectrode Array
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Si Nanowires
Ultrahigh piezoresistance of Si nanowire sensor
application, actuator, microscope cantilever, etc.
A Si nanowire MOSFET
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Si Nanowire Growth
Vapor-Liquid-Solid mechanism Si nanowire
growth. Difference between Si nanowire and CNT
CNT is hollow, but Si nanowire is solid with
crystalline core.
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Si Nano Wire Transistors
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Nanowire-based Vertical Gate Transistor
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ZnO Nanowires
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Challenges of Nanowire Growth
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Challenges of Nanowire Growth
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Nanoelectronics Now or Never?" IEDM Evening
Panel Discussion, December 14,
Session 26 800 p.m. Continental Ballroom 6-9
Moderator Mark Lundstrom, Purdue University
"Nanoelectronics Now or Never?" Traditional
'top-down' microelectronics has become
nanoelectronics with device dimensions comparable
to those being explored in the new field of
ëbottom-up' nano- and molecular electronics. We
use the terms, top-down and bottom-up, in a very
general sense. Top-down refers to a way of
thinking and building that begins at the macro
(continuum) scale and pushes to the nanoscale.
Bottom-up refers to a way of thinking and
building that begins at the atomistic level and
builds up to the nanoscale. The top-down approach
has already delivered silicon MOSFETs with
channel lengths of 5nm, but scaling down device
dimensions with commensurate increase in device
and system performance is increasingly
challenging. Bottom-up technology has
demonstrated molecular switches, nanotube and
nanowire FET's, NDR and single electron devices,
and ultra-dense memory prototypes. Is bottom-up
nanotechnology ready to address the industry's
challenges, or is it still long-term research
with essentially unpredictable outcomes? This
panel will debate the question of what the
intersection of top-down and bottom-up
electronics will mean to semiconductor technology
of the future.