Design for Reuse in embedded system design

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Design for Reuse in embedded system design

• Seminar
• Design of Systems-on-a-chip for communication
  applications

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Agenda

• Introduction
• Reusability and Design
• Standards and Tools
• Research Topics
• Conclusions

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1.Introduction

• What is an embedded system?
• A special-purpose computer built into and
  integral to a device.

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1.Introduction

• Systems-on-a-chip

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1.Introduction

• Potential vs. Productivity

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1.Introduction

• Systems-on-a-chip
• Nearly boundless transistor capacity on ICs
• Conventional design techniques are not adequate
• New design challenges emerge
• Complex designs
• Increase level of abstraction
• Time to market

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Agenda

• Introduction
• Reusability and Design
• Standards and Tools
• Research Topics
• Conclusions

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2. Design and Reusability

• Higher level of Abstraction
• Reach more complexity
• Dont think about implementation details
• Example
• Software
• RISC vs. CISC
• Reliable compilers
• Hardware
• Synthesis

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2. Design and Reusability

• What is the difference in SoC Design?

Block Selection/ design
Time to market
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2. Design and Reusability

• If a previous designed-blocks library is
  available

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2. Design and Reusability

• A design must be first usable.
• Design for use requires
• Good documentation
• Good code
• Through commenting
• Well-designed verification environments and
  suites
• Robust scripts

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2. Design and Reusability

• Design Reuse
• The ability to retarget previously designed
  building blocks or cores on a chip for a new
  design in order to reduce time to market

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2. Design and Reusability

• Design for Reuse requires
• Designs oriented to solve general problems
• Flexibility
• Use in multiple technologies
• Simulation with different simulators
• Independent and rigorous verification
• Full documentation

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2. Design and Reusability

• Basic units
• IP Blocks (also called cores, virtual components,
  macros)
• Pre-designed, pre-verified complex functional
  blocks.
• Hard cores
• (black boxes, layout level, certain silicon
  process)
• Soft cores
• (white boxes, RTL level)
• Firm cores
• (grey boxes, configurable i/o,)

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2. Design and Reusability

• The Development Tree

Hardcores
Implementation
Layout (aspect ratio, cell positions)
Description (Diagram, HDL)
Specification
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2. Design and Reusability

• Reusability is not a new method
• J. S. Bachs composition method (XVIII century)
• Not based on single notes
• Figures
• Corta
• Groppo
• Tirata
• Pre-designed structures
• High complex compositions
• Problem
• How to harmonise together the figures?

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2. Design and Reusability

• Fundamental Problems for Reuse
• Blocks not in appropriate representation
• Incomplete design information
• Disperse Designs
• Unavailable tools
• Simulation not viable
• In other words
• Designing systems without thinking on reusability
• Possible Solution
• Observe Standards and use adequate tools

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Agenda

• Introduction
• Reusability and Design
• Standards and Tools
• Research Topics
• Conclusions

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3. Standards and Tools

• Virtual Socket Interface Alliance (VSIA)
• Facilitates adoption of design reuse
• Sets Standards for tool Interfaces and design
  practices
• Architecture document
• User guide
• System and logic design
• Test requirements
• Physical implementation

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3. Standards and Tools

• Motorolas Semiconductor reuse Standard
• http//e-www.motorola.com/technology/srs/
• IP/VC block deliverables
• Data to develope and formats
• IP Interface
• Rapid SoC integration
• Verilog HDL coding
• Based on IEEE 1364.1 Verilog subset
• Documentation
• IP creation, use, integration and Tests

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3. Standards and Tools

• OpenMORE
• Open Measure of Reuse Excellence
• Free Web-Based measurement tool
• Developed by Synopsys and Mentor Graphics
• Based on the Reuse Methodology Manual (RMM)
• Donation to VSIA on June 18th 2001
• http//www.openmore.com/openmore/download.cfm

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3. Standards and Tools

• OpenMORE
• What is required to produce one core?
• How difficult is to integrate certain core?
• Used for
• Developing reuse infrastructure
• Key and deliverable specification
• Evaluate intellectual property using Guidelines
• 150 for softcores
• 90 for hardcores

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3. Standards and Tools

• OpenMORE
• Grading process
• Maximum points
• 730 for softcores
• 530 for hardcores
• Guidelines Categories
• Macro Design
• Verification
• Deliverables
• Ratings in Synopsys Catalyst catalogues

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3. Standards and Tools

• AMBA Bus
• Open Standard on Chip specification
• Reusable design methodology
• Common backbone for SoC modules

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3. Standards and Tools

• CoreConnect Bus Architecture
• Foundation of IBM Blue Logic
• 32- and 64- bit architecture versions
• Separate read-write data buses.

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Agenda

• Introduction
• Reusability and Design
• Standards and Tools
• Research Topics
• Conclusions

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5. Research topics

• IP component description for multi-media
  applications

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5. Research topics

• Behavioural hardware reuse
• Using C for SoC design
• Usually done at structural level

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Agenda

• Introduction
• Reusability and Design
• Standards and Tools
• Research Topics
• Conclusions

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6. Conclusions

• Reuse permits complex designs
• Reuse attitude is required
• Design thinking on reusability
• IP blocks must be easy to use
• Well designed re-usable IP components enable
  successful SoC integration