Research on 3D Parasitic Extraction and Interconnect Analysis

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Research on 3-D Parasitic Extraction and
Interconnect Analysis

• Wenjian Yu
• EDA Lab, Dept. of Computer Science Technology,
  Tsinghua University
• Beijing, P. R. China

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Outline

• Background
• BEM Solver for Capacitance/ Resistance Extraction
• Frequency-Dependent Reluctance / Impedance
  Extraction
• Substrate Parasitic Extraction
• Other Works on Interconnect Modeling/ Analysis

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Background

• Parasitic extraction in deep-submicron VLSI
• Interconnect dominates circuit performance
• Interconnect delay gt device delay
• Crosstalk, signal integrity, power, reliability
• Other parasitics in SOC
• Substrate coupling in mixed-signal circuit

• Interconnect parasitic extraction
• Resistance, Capacitance and Inductance
• Becomes a necessary step for performance
  verification in the iterative design flow
• Parasitic parameters should be extracted
  accurately

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From electro-magnetic analysis to circuit
simulation
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Background

• Research Focus
• Fast numerical methods for 3-D field solver
• Considering emerging problems for interconnect
  modeling and analysis
• Team Collaboration
• 1 Ph.D student, 3 master students
• 2 undergraduates/spring semester
• Collaborate with Prof. Hongs team
• With Prof. Z. Yus team at IME of Tsinghua Univ.
• With Prof. C-K Chengs team at UCSD

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Outline

• Background
• BEM Solver for Capacitance/ Resistance Extraction
• Frequency-Dependent Reluctance / Impedance
  Extraction
• Substrate Parasitic Extraction
• Other Works on Interconnect Modeling/ Analysis

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QBEM - QMM accelerated BEM

• Features of QBEM
• 3D field solver in the LPE flow
• Has similar input format to Raphael RC3
• Same boundary assumption as Raphael
• Several tens to hundreds faster thanRaphael 10x
  faster than FastCap
• Algorithms inside
• Based on the multi-zone boundary element
  analysis.
• The original dielectrics are cut into fictitious
  medium regions, to maximize the sparsity of
  matrix A (Axb is solved).
• Efficient techniques of storing sparse matrix and
  Krylov iterative solver are used to exploit the
  matrix sparsity for performance improvement.

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QBEM - QMM accelerated BEM
A 3-D multi-dielectric case for capacitance
extraction
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QBEM - QMM accelerated BEM

• Handling of complex structures
• Bevel conductor line conformal dielectric
• Structure with floating dummy fill
• Multi-plane dielectric in copper technology
• Metal with trapezoidal cross section

• 3-D resistance extraction
• Complex 3-D structure with multiple vias
• Improved BEM coupled with analytical formula
• Extract DC resistance network
• Hundreds/thousands times fast thanRaphael, while
  maximum error lt3

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HBBEM Hierarchical Block BEM

• Features of HBBEM
• 3D field solver for capacitance extraction
• Same BEM kernel as QBEM, but directly get the
  capacitance matrix, without setting bias voltages
  for many times
• Faster than QBEM for matrix extraction
• Extension Application
• Full-chip parallel extraction, combined with an
  overlap-combination approach
• Employed by CSurfIBMs primary 3-D solver

Partition of 3-D Structure
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Relevant publications

• W. Yu, Z. Wang, J. Gu, Fast capacitance
  extraction of actual 3-D VLSI interconnects using
  quasi-multiple medium accelerated BEM, IEEE
  Trans. Microwave Theory Tech., Jan 2003 , 51(1)
  109-120
• W. Yu, Z. Wang, Enhanced QMM-BEM solver for 3-D
  multiple-dielectric? capacitance extraction
  within finite domain, IEEE Trans. Microwave
  Theory Tech., Feb 2004, 52(2) 560-566
• X. Wang, D. Liu, W. Yu, Z. Wang, Improved
  boundary element method for fast 3-D interconnect
  resistance extraction, IEICE Trans. on
  Electronics, Feb. 2005, E88-C(2) 232-240
• M. Zhang, W. Yu, Z. Wang, Efficient 3-D
  extraction of interconnect capacitance
  considering floating metal-fills with boundary
  element method, IEEE Trans. Computer-Aided
  Design, Jan 2006, 25(1) 12-18
• T. Lu, Z. Wang, W. Yu, Hierarchical block
  boundary-element method (HBBEM) A fast field
  solver for 3-D capacitance extraction, IEEE
  Trans. Microwave Theory Tech., Jan. 2004, 52(1)
  10-19

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Outline

• Background
• BEM Solver for Capacitance/ Resistance Extraction
• Frequency-Dependent Reluctance / Impedance
  Extraction
• Substrate Parasitic Extraction
• Other Works on Interconnect Modeling/ Analysis

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Background of inductive effect

• Inductive effects becomes increasingly
  significant
• Long metal interconnects
• Higher clock frequency
• Reduction in on-chip resistance and capacitance
  (copper, wider upper-layer metal, low-k
  dielectric)
• Frequency-dependent inductance / impedance
• High-frequency skin effect and proximity effect
• Model off-chip structures, or
• on-chip high-lever wide interconnects
• Different electromagnetic analysis MQS, EMQS,
  full-wave
• Methods PEEC(volume discretization), BEM, FEM

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Reluctance (K) extraction

• Reluctance is the inverse of partial inductance
• K was proposed by Devgan et. al (ICCAD2000) K
  L-1
• Has the locality property like capacitance
• Easily sparsified for acceleration of extraction
  and simulation
• Frequency-dependent reluctance extraction
• General window technique
• Efficient intra-window extraction
• Directly extract K without inversion from L
• Matrix condensation and GMRES solution
• Reuse of filament inductances
• At least 50 times faster than FastHenryfor
  off-chip structures, or on-chip P/G nets

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BEM-based impedance extraction

• BEM has some advantages over volume
  discretization
• Surface discretization, independent of frequency
• Extends to full-wave analysis
• MIT proposed FastImp based on BEM
• Our work
• A reuse scheme of the boundary integrals in
  FastImp for multi-frequency extractionshows 2 -3
  times speedup
• Mixed BEM which combines the direct BIE with an
  indirect BIE for conductor domain
• Reduce unknown from 7N to 4N
• About 2 times faster than FastImp

Full wave
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Relevant publications

• Papers
• M. Zhang, W. Yu, Y. Du, Z. Wang, An efficient
  algorithm for 3-D reluctance extraction
  considering high frequency effect, ASP-DAC 2006,
  Japan, Jan. 2006, pp. 521-526
• C. Yan, W. Yu, Z. Wang, Application of the
  complete multiple reciprocity method for 3D
  impedance extraction with multiple frequency
  points, Engineering Analysis with Boundary
  Elements, Aug. 2006, 30(8) 640-649
• W. Yu, C. Yan, Z. Wang, A mixed surface integral
  formulation for frequency-dependent inductance
  calculation of 3D interconnects, Engineering
  Analysis with Boundary Elements, 2007, 31(10)
  812-818
• F. Gong, W. Yu, et. al, Efficient techniques for
  3-D impedance extraction using mixed boundary
  element method accepted by ASP-DAC2008

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Outline

• Background
• BEM Solver for Capacitance/ Resistance Extraction
• Frequency-Dependent Reluctance / Impedance
  Extraction
• Substrate Parasitic Extraction
• Other Works on Interconnect Modeling/ Analysis

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BEM-based substrate extraction

• Substrate coupling in mixed-signal IC
• flt GHz, resistive coupling is primary
• Higher frequency, both resistive and capacitive
  (even L) coupling are considered
• Problem solved with BEM
• Resistive model
• Plate contact, multi-layer substrate,substrate
  with lateral resistivity variation
• Analog of capacitance extraction
• Steady current field
• Three kinds of boundary
• Extend to resistive capacitive model
• Introduce complex-valued conductivity

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BEM-based substrate extraction

• subDBEM
• Non-uniform element partition
• Condense linear system
• QMM technique
• Several or tens times faster than Greens
  function based method reported in literatures
• Easily handle non-stratified substrate
• subRCbem
• Calculate equivalent Z considering R, C coupling
• A two-step approach for multiple frequencies
• For each frequency, only solve a matrix whose
  order is the number of elements on layer
  interface
• Experiments exhibit advantages over ASITIC of UCB

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Relevant papers

• Z. Ye, W. Yu, Z. Yu, Efficient 3D capacitance
  extraction considering lossy substrate with
  multi-layered Greens function, IEEE Trans.
  Microwave Theory Tech., May 2006, 54(5)
  2128-2137
• X. Wang, W. Yu, Z. Wang, Efficient direct
  boundary element method for resistance extraction
  of substrate with arbitrary doping profile, IEEE
  Trans. Computer-Aided Design, Dec. 2006, 25(12)
  3035-3042
• W. Yu, X. Wang, Z. Ye, Z. Wang, Efficient
  extraction of frequency-dependent substrate
  parasitics using direct boundary element method,
  submitted to IEEE Trans. Computer-Aided Design

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Outline

• Background
• BEM Solver for Capacitance/ Resistance Extraction
• Frequency-Dependent Reluctance / Impedance
  Extraction
• Substrate Parasitic Extraction
• Other Works on Interconnect Modeling/ Analysis

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Other works on interconnect

• Capacitance extraction considering process
  variation
• Consider window-based chip-level extraction
• Propose technique for inter-window capacitance
  covariance induced by spatial correlation
• Practical for full-chip or full-path
  variation-aware extraction
• Transient simulation through frequency domain
• Solve for frequency-domain response
• Rational approximation using vector fitting
• Applied to analysis of P/G grid and clock network
  
• Eye-diagram prediction for LTI system
• Predict the worst-case metrics of signaling
  quality, like eye-opening voltage, timing jitter,
  from the systems step response
• Used in transmission line design

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Relevant papers

• Papers
• W. Zhang, W. Yu, et. al, An efficient method for
  chip-level statistical capacitance extraction
  considering process variations with spatial
  correlation, accepted by DATE 2008
• L. Zhang, W. Yu, et. al, Clock skew analysis via
  vector fitting in frequency domain, accepted by
  ISQED2008
• W. Yu, R. Shi, et. al, Accurate eye-diagram
  prediction and its application for off-chip
  signaling schemes, submitted
• L. Zhang, W. Yu, et. al, Low power passive
  equalizer optimization using tritonic step
  response, submitted

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Thank you!

• Yu-wj_at_tsinghua.edu.cn