:: Milestone 5 2D Discrete Cosine Transform

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Milestone 5 2-D Discrete Cosine Transform

• Group M2
• Tommy Taylor
• Brandon Hsiung
• Changshi Xiao
• Bongkwan Kim
• Project Manager Yaping Zhan

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Team Paradigm
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Project status

• Design Proposal (Complete)
• Architecture Proposal (Complete)
• Behavioral Verilog and test bench (Done)
• Schematic (Done)
• Verilog verification of full-chip schematic
  (done)
• Component layout
• Registers, Adder/Subtractor (done)
• SRAM (70 done)
• MUX, counters ?
• ROMs ?

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XOR
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Registers
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Single Bit Register
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16bit Register
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16bit Register Closeup
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MUX
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21 mux
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16 bit 21 mux
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16 bit 21 mux closeup
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Adder Subtractor
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Mirror Adder
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16bit Adder
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Mirror Adder 16bit Closeup
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Subtractor

• Adder with input inverted...and first bit carry
  in set to gnd.

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64x16 Dual Port SRAM
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64x16 dual port SRAM --- basic cell schematic
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64x16 dual port SRAM --- basic cell layout
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64x16 dual port SRAM --- sense amplifier schematic
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64x16 dual port SRAM --- sense amplifier layout
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64x16 dual port SRAM --- precharge circuitry
schematic
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64x16 dual port SRAM --- precharge circuitry
layout
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SPICE simulation of 1 bit, 2 words, dual port SRAM
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SPICE simulation of 1 bit, 2 words, dual port
SRAM results
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SPICE simulation of 1 bit, 2 words, dual port
SRAM results
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64x16 dual port SRAM --- row decoder schematic
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64x16 dual port SRAM --- core layout
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Floor plan Proposal
200u
500u
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Overall floorplan
150
1D DCT
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500
16 x 64 SRAM
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1D DCT
500
500 x 600 300,000um2
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Questions ?