SNS

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• SNS
• PCI Data Acquistion
• Timing Decoder
• Joe Mead

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Overview

• PCI card history
• Requirements
• Differences from LANL PCI card
• Similiarities to ORNL Embedded Timing Card
• Implementation
• Status

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PCI data acquisition card history

• Currently using LANL PCI card
• Loss of support from LANL as manpower has been
  shifted to LLRF.
• Unable to get more PCI cards from LANL, resorted
  to making their boards ourselves from Gerber
  files.
• Due to this lack of support plus newer design
  requirements we have designed our own PCI card
  which is based on the ORNL embedded timing card.

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Requirements

• Provide PCI Data Acquisition Control Interface
  for BCM, BPM and Tune electronics
• Data Acquisition
• Decode Triggers from Event Link (Tzero, etc.)
• Decode Timestamp from RTDL
• Provide programmable delay for Tzero trigger
• Buffer digitized data into local SRAM memory
• DMA buffered data out over PCI

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Requirements

• Provide PCI Data Acquisition Control Interface
  for BCM, BPM Tune electronics
• Front End Control
• Programmable Gain
• Calibrator
• RF Synthesizer
• kick output

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Differences from LANL PCI Card

• Integrate event link RTDL decoder
• In-system programmable FPGA
• Replace 4 expensive FIFOs (600) with 2 - SSRAM
  (30) with 2x capacity
• Integration of front-end control requirements
  (gain, calibrator, RF-synthesizer, etc.)

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Similiarities to ORNL Embedded Timing Card

• Design is superset of Oak Ridge Embedded Timing
  PCI Card.
• Same event link RTDL decoders
• Same In-system programmable FPGA
• Same PCI interface (Altera PCI Core)
• Added SRAM buffer and Front-End Interface

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Buffer Depth - BPM

• Number of channels 4
• Number of bits 16
• Max sample rate 68MS/s
• Single shot storage time 1.6ms
• Memory Size Required
• 4ch 2bytes 1.6ms 68MS/s 870Kbytes
• Memory On-board 2Mbyte

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Buffer Depth - BCM

• Number of channels 2
• Number of bits 16
• Max sample rate 68MS/s
• Single shot storage time 1.6ms
• Memory Size Required
• 2ch 2bytes 1.6ms 68MS/s 435Kbytes
• Memory On-board 2Mbyte

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PCI Data Throughput Requirements

• DMA from local memory to system memory _at_ 6Hz
• - BPM
• 870Kbytes _at_6Hz 5.22Mbytes/sec
• - BCM
• 435Kbytes _at_ 6Hz 2.61Mbytes/sec
• PCI Max throughput 132Mbytes/sec
• PCI typ throughput 60Mbytes/sec

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Event Link Decoder

• PLL front end based on V124S design
• Output of PLL circuit is 34Mhz clock, serial data
  stream and lock signal.
• Event Decoding done in FPGA state machine

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RTDL Decoder

• Delay line front end
• Same design used by Utility module
• Output of delay line circuit
• Clock
• 32 bit parallel word
• Data valid strobe

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Block Diagram
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Status

• Currently in Layout
• Expect first prototype in 4-6 weeks