Low power SoC platform Trend

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Low power SoC platformTrend Futureworks

• 2004. 2. 6.
• Super computing Lab.
• Park, Jung-Wook

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Contents

• SoC concept issue
• Lowpower techniques
• System level power management in SoC platform
• Microarchitecture level lowpower technic
• Related works
• Future works

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SoC

• ASIC
• System on a chip
• Design process
• Products
• IP

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SoC issues

• Increased complexity
• Large system
• IP reuse
• HOT
• Reusability test, verification
• COOL
• Low power issue

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Why Low Power?

• Thermal problem in high-end
• Battery limitation in low-end mobile embedded

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HW design level
system
Architecture
Micro-architecture
RT-level
Circuit-level
Device-level
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Low power techniques
Low power
RT-level
uArch-level
Optimization
Optimization
Dynamic Power management
Dynamic Power management
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RT-level power management

• DVS
• Supply lower voltage -gt increased latency
• Additional circuits for delayed timing
• DFS
• Clock frequency control
• Overall energy cannot be reduced

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OS supported DVS

• Interval(temporal) based
• Strong point
• Can get similar DVS curve with CPU Utilization
• Week point
• Cannot distinguish an urgent task that must run
  at full speed to meet a tight deadline from a
  less important task with several milliseconds to
  complete and little work to do

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OS supported DVS cont.

• Task based
• Strong point
• Task know about peak power, so optimal DVS can be
  executed.
• Week point
• Systems do not generally have definite knowledge
  of task CPU requirements .

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PowerPC 405LP

• Supporting S/W control

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ARM

• Dynamic energy management (SW/HW cooperate)

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Microarchitecture level power management(1/2)

• Processor
• Various reconfigurable low power mechanism
• Cache, register, buffers, pipeline, IU etc.
• Bus
• Reconfigurable bandwidth
• SoC
• System level power performance evaluation

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Microarchitecture level power management(2/2)

• Parameterization
• Power-Performance trade-off factor
• Optimal points for applications
• Reconfigurablity
• Adaptive processing
• System level energy management without varing
  clock

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Parameterization

• Processor
• Operating frequency
• cache, branch predictor ..etc.
• IP
• Bus bandwidth
• Identical properties on each functional block

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Related works (1/2)

• University of California, Riverside
• Cache -gt SoC
• Parameterization
• Bus bandwidth and Cache
• Analyzing optimal setting for system
• Simulation environments
• C-based system simulator
• RT-level implement

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Related works (2/2)

• Adaptive processing
• Monitoring
• Feedback and control

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Lowpower SoC platform

• Lowpower control core and reconfigurable blocks

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Future works

• Adaptive process SoC platform for low power
• Architecture for monitoring, feedback control
• Application (IP) analyzing method
• Reconfigurable IPs
• Reconfigurable interconnection (support for
  reconfigurable block)
• Reconfigurable memory management
• Flexible cache allocation
• Scheduling decision algorithm for power control
  core

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Static vs Dynamic approach

• Static analyze Static adaptation
• Static analyze Dynamic adaptation
• Dynamic analyze Dynamic adaptation

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System-level simulator(1/2)

• Simulator based on C
• CPU, bus and other Ips
• SystemC
• Required for
• Fast simulation
• Fast adaptation of new theory
• Analysis of various statistics

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System-level simulator(2/2)

• Opencore simulator
• OR1200 processor
• Wishbone bus
• Several IPs with device driver
• uCLinux ported
• 32-bit SoC simulator
• Riverside
• MIPS based (digital camera example)
• SIMICS
• Full system

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IC development tool

• Simulator
• Behavioral modeling
• ModelSim
• Synthesizer
• Gate-level synthesize
• Synopsis, Leonardo
• Implementation
• FPGA
• Excaliver

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System development tools for SoC

• MAX-SIM, MAX-CORE (AXYS)
• Fast, Accurate
• System simulator
• IDEC ?? ?? (3??)