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Chapter 8 68HC11 Timer Functions
The 68HC11 Microcontroller
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Applications that Requires a Dedicated Timer
System - delay creation and measurement - period
measurement - event counting - time-of-day
tracking - period interrupt generation to remind
the processor to perform routine tasks - waveform
generation - etc.

• A Summary of the 68HC11 Timer Functions
• 1. Main timer
• 16-bit non-stop timer
• read-only after reset
• 2. Input capture function
• three channels -- 1 to 3
• each channel has a 16-bit latch, edge-detection
  logic, flag bit, and interrupt logic
• will load the current main timer value into the
  input capture register when the selected
• signal edge is detected
• can be used to measure the signal frequency,
  period, and pulse width and as time reference

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• 3. Output compare functions
• five channels (OC1OC5)
• each channel has a 16-bit comparator, 16-bit
  register, action pin, interrupt request circuit,
• forced-compare function
• continuously compare the value of the 16-bit
  compare register with that of the main timer
• and may optionally trigger an action on a pin,
  generate an interrupt
• is often used to create a delay and generate a
  waveform
• 4. Real-time interrupt
• generates periodic interrupts when enabled
• interrupt period is programmable
• 5. Computer operating properly (COP)
• discussed in Chapter 5
• 6. Pulse accumulator

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The Free-Running Main Timer (TCNT)
TOI
Interrupt request
TOF
Prescaler divided by 1, 4, 8, or 16
TCNT (L)
TCNT (H)
MCU E clock
16-bit free-running counter
Taps for RTI, COP watchdog, and pulse accumulator
Figure 8.1 68HC11 Main timer system circuit
7 6 5 4
3 2 1
0
TOI RTII PAOII PAII 0
0 PR1 PR0
TMSK2
value after reset
0 0 0 0
0 0 0
0
TOF RTIF PAOVF PAIF
TFLG2
value after reset
0 0 0 0
0 0 0
0

• The main timer is cleared to 0 on reset and is
  read-only except in test mode.
• The timer overflow flag (TOF) in timer flag
  register 2 (TFLG2) will be set to 1 when the
• count changes from FFFF to 0000.
• The TOF flag can be cleared by writing a 1 to
  it.
• An interrupt may be generated if the timer
  overflow interrupt enable bit (TOI) in the
• timer mask register 2 (TMSK2) is set to 1.
• The timer counter register is meant to be read
  by a 16-bit read instruction such as LDD or
• LDX.

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The prescale factor for the main timer is
selected by bits 1 and 0 of the timer mask
register 2 as shown in Table 7.1
Table 8.1 Main timer clock frequency Vs. PR1 and
PR0 values
overflow period
prescale 2 MHz 1 MHz PR1
PR0 factor E clock E
clock
0 0 1 32.77
ms 65.54 ms 0 1 4
131.1 ms 262.1 ms 1 0
8 262.1 ms 524.3
ms 1 1 16 524.2
ms 1.049 s
Example 8.1 What values will be in A and B after
execution of the following three instructions if
TCNT contains 5EFE when the upper byte is
accessed ? Assume the bits PR1 and PR0 of TMSK2
are 00. regbas equ 1000 TCNTH equ
0E TCNTL equ 0F ldx regbas ldaa
TCNTH,X read the upper byte of TCNT ldaa
TCNTL,X read the lower byte of TCNT
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Solution - The main timer prescale factor is 1
and hence the E clock is the clock input to
TCNT. - The instruction LDAA TCNTH,X loads the
upper byte (value is 5E) of TCNT into A. - The
instruction LDAB TCNTL,L takes 4 E clock cycles
to execute. Therefore, TCNT will have been
incremented by 4 to 5F02. The accumulator B
will receive the value 02. This is not what we
expect. If the instruction LDD TCNT,X is
executed, then A and B will contain 5E and FE
respectively.
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Input Capture Functions - Physical time is
often represented by the contents of the main
timer. - The occurrence of an event is
represented by a signal edge (rising or falling
edge). - The time when an event occurs can be
recorded by latching the count of the main
timer when a signal arrives.
Rising edge
Falling edge
or
Figure 8.1 Events represented by signal edges
- The 68HC11 has three input capture channels
(IC1, IC2, IC3) to implement this
operation. - Each input capture channel has a
16-bit input capture register, a flag,
edge-detection logic, and interrupt request
circuit.
Interrupt request
ICxI
Pins PA2, PA1, PA0 are used for input
capture functions.
Edge-detection logic
ICx pin
16-bit latch
ICxF
TICx
Figure 8.4 Input-capture function block diagram
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- The edge to be captured is selected by
programming the register TCTL2.
TCTL2
EDG1A EDG1B EDG2A EDG2B EDG3A EDG3B
value after reset 0 0
0 0 0 0
EDGxB EDGxA 0 0 capture
disabled 0 1 capture on
rising edge 1 0 capture
on falling edge 1 1
capture on both edges x 1,2,3
For example, the following instruction sequence
captures the rising edge of the signal applied at
PA0 (IC3) regbas equ 1000 TCTL2 equ 21
offset of TCTL2 from regbas ldx
regbas bclr TCTL2,X 00000010 clear bit 1
to 0 bset TCTL2,X 00000001 set bit 0 to 1
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- Registers related to input capture
- the lowest three bits (bits 2 to 0) of this
register enable/disable the interrupt from the
proper input capture channel - the upper five
bits (bits 7 to 3) of this register
enable/disable the interrupt from
the corresponding output compare channels
2. timer flag register 1 (TFLG1)
7 6 5 4
3 2 1
0
OC1F OC2F OC3F OC4F OC5F
IC1F IC2F IC3F
0 0 0 0
0 0 0
0
- the lowest three bits (bits 2 to 0) of this
register are input capture flags - the arrival of
a signal edge will set one of the input capture
flags - the upper five bits (bits 7 to 3) of this
register are output compare flags
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How to clear a timer flag bit? - write a 1 to
the flag bit to be cleared - use the BCLR
instruction with a 0 at the bit position (s)
corresponding to the flag (s) to be cleared.
For example, BCLR TFLG1,X FE will clear
the IC3F flag. (Assume the index register
contains 1000 and TFLG1 23) - load an
accumulator with a mask that has a 1 (or 1s) in
the bit (s) corresponding to the flag(s) to be
cleared then write this value to TFLG1 or TFLG2.
For example, LDAA 01 STAA
TFLG1,X will clear the IC3F flag.
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Applications of Input Capture function - Event
arrival time recording - Period measurement the
input capture function captures the main timer
values corresponding to two consecutive rising
or falling edges
one period
(a) capture two rising edges
one period
(b) capture two falling edges
Figure 8.8 Period measurement by capturing
two consecutive falling or rising edges
- Pulse width measurement capture the rising and
falling edges
pulse width
Figure 8.9 Pulse-width measurement using input
capture function
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- Interrupt generation three input capture
functions can be used as three edge-sensitive int
errupt sources. - Event counting by counting the
number of signal edges arrived during a period
ei
e1
e2
e3
ej
..
start of interval
end of interval
Figure 8.10 Using an input capture function for
event counting
- Time reference often used in combination with
an output compare function
time t0
time t0 delay
time to activate output signal (set up by output
compare)
time of reference (set up by signal edge)
Figure 8.11 A time reference application
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Output Compare Functions - five output compare
channels OC1-OC5 - port A pins PA7-PA3 are
associated with output compare channels OC1-OC5
respectively - Each output compare channel
consists of 1. a 16-bit comparator 2. a 16-bit
compare register (TOCx, x 1,,5) 3. an output
action pin 4. an interrupt request circuit 5.
a forced-compare function (FOCx, x 1,,5) 6.
control logic
interrupt request
OCxI
16-bit comparator
OCxF
TOCx
Pin control logic
OCx Pin
x 1,,5
FOCx
Figure 8.16 Output-compare function block diagram
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- To use an output compare function, 1. make a
copy of the main timer 2. add to this copy a
value equal to the desired delay 3. store the
sum onto an output-compare register - The
actions that can be activated on an output
compare pin include 1. pull up to high 2. pull
down to low 3. toggle The action is determined
by the timer control register 1 (TCTL1)
7 6 5 4
3 2 1
0
OM2 OL2 OM3 OL3 OM4
OL4 OM5 OL5
value after reset
0 0 0 0
0 0 0
0
OMx OLx 0 0 OCx does not affect pin
0 1 Toggle OCx pin on successful
compare 1 0 Clear OCx pin on
successful compare 1 1 Set OCx pin on
successful compare x 2,,5
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Using OC1 to Control Multiple OC Functions - OC1
can control up to five OC pins - The OC pins to
be controlled by OC1 are specified by the
register OC1M. - The value that any OCx (x
1,,5) pin to assume when the value of TOC1
equals TCNT is specified by the OC1D register.
- When a successful OC1 compare is made, each
affected pin assumes the value of
the corresponding bit of OC1D.
7 6 5 4
3 2 1
0
OC1M
M7 M6 M5 M4
M3 0 0 0
value after reset
0 0 0 0
0 0 0
0
pin controlled
PA7 OC2 OC3 OC4 OC5
7 6 5 4
3 2 1
0
OC1D
D7 D6 D5 D4
D3 0 0 0
value after reset
0 0 0 0
0 0 0
0
- The OC1 (PA7) pin is bidirectional. For this
pin to be controlled by OC1 function, it must be
configured for output. The direction of PA7 pin
is controlled by the bit 7 of the
PACTL register. Set bit 7 of PACTL to 1 to
configure PA7 pin for output.
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Example 8.9 Write values into OC1M and OC1D so
that OC2 and OC3 pins will assume the values of
0 and 1 when the OC1 compare operation
succeeds. Solution
- Set bits 6 and 5 of OC1M to 11 - Set bits 6
and 5 of OC1D to 01 regbas equ
1000 OC1M equ 0C OC1D equ 0D ldx
regbas ldaa 01100000 staa OC1M,X ldaa
00100000 std OC1D . . .
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Forced Output Compare - useful when the user
requires the output compare to succeed
immediately after being started - write a 1 to
the corresponding bit of the CFORC register to
force an output compare operation - The forced
output compare operation only causes pin action.
Neither the flag is set to 1 nor the interrupt
is generated.
7 6 5 4
3 2 1
0
CFORC
FORC1 FOCR2 FORC3 FORC4 FORC5 0
0 0
value after reset
0 0 0 0
0 0 0
0
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Example 8.12 Suppose that the contents of the
TCTL1 register are 10011000. What would occur
on pins PA6-PA3 on the next clock cycle if the
value 01111000 is written into the CFORC
register? Solution The contents of TCTL1
configure the output compare actions in Table 7.5
Table 7.5 Pin actions on OC2-OC5
Bit positions Value Action to be triggered
7 6 10 clear PA6 5 4 01 toggle
PA5 3 2 10 clear PA4 1 0 00 no
effect
- CFORC specifies that OC2-OC5 are to be
forced. - Pin PA6 will be pulled low - Pin PA5
will be toggled - Pin PA4 will be pulled
low - Pin PA3 will not be affected
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Real-Time Interrupt (RTI) - will generate
periodic interrupts if enabled. - The RTI
interrupt period is programmable by programming
the bits 1 and 0 of the PACTL register.
Table 7.6 RTI clock source prescale factor
RTR1 RTR0 bit 1 bit 0 (E 213)
divided by
0 0 1 0
1 2 1 0 4 1 1 8
- RTI interrupt is enabled by setting the bit 6
of the TMSK2 register - The bit 6 of the TFLG2
register will be set to 1 on a RTI interrupt
Example 8.13 Use the RTI function to create a
delay of 10 seconds. Solution - select the
prescale factor of 8 which will set the interrupt
period to 32.67 ms - need to enable RTI
interrupt - 305 RTI interrupts will roughly
create a delay of 10 seconds
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regbas equ 1000 TMSK2 equ 24 TFLG2 equ
25 PACTL equ 26 tensec equ 305 total RTI
interrupts in 10 s RTIF equ 40 mask to select
the RTIF flag org 0000 rti_cnt rmb 2
remaining RTI interrupts to be generated org
00EB RTI interrupt vector jump table
entry jmp rti_hnd org C000 lds 3F
initialize stack pointer ldx regbas ldd
tensec std rti_cnt bset PACTL,X 03 select
RTI clock prescale factor to 8 ldd RTIF staa
TFLG2,X clear RTIF flag staa TMSK2,X enable
RTI function cli enable interrupt to the
68HC11 loop ldd rti_cnt wait until rti_cnt
becomes 0 bne loop . . .
RTI service routine is as follows rti_hnd
ldx regbas bclr TFLG2,X BF ldx
rti_cnt dex stx rti_cnt rti
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The Pulse Accumulator - 8-bit pulse accumulator
(PACNT) - two operation modes event counting and
gated accumulation modes - PACNT is clocked by
the PAI input in event counting mode - PACNT is
clocked by the E-divided-by-64 clock in gated
accumulation mode - The PAI pin (PA7 pin) must be
configured for input to enable pulse
accumulator - There are two interrupt sources
PAI pin edge and the rollover of PACNT from FF
to 00 - Four registers are related to the
operation of the PACNT TMSK2, TFLG2, PACTL, PACNT
7 6 5 4
3 2 1
0
TMSK2
TOI RTII PAOVI PAII 0
0 PR1 PR0
value after reset
0 0 0 0
0 0 0
0
7 6 5 4
3 2 1
0
TFLG2
TOF RTIF PAOVF PAIF 0
0 0 0
value after reset
0 0 0 0
0 0 0
0
7 6 5 4
3 2 1
0
PACTL
DDRA7 PAEN PAMOD PEDGE 0 0
RTR1 RTR0
value after reset
0 0 0 0
0 0 0
0
7 6 5 4
3 2 1
0
PACNT
bit 7 bit 6 bit 5 bit 4
bit 3 bit 2 bit 1 bit 0
value after reset
- - - -
- - -
-
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- The bits 5 and 4 of TMSK2 enables/disables
PACNT overflow and PAI edge interrupt
respectively. - The bits 5 and 4 of TFLG2 are
pulse accumulator overflow and PAI edge flag
respectively.
The Pulse Accumulator Control Register
(PACTL) - bit 7 (DDRA7) 0 -- configure PA7 pin
for input 1 -- configure PA7 for output - bit 6
(PAEN) 0 -- disable PA function 1 -- enable PA
function - bit 5 (PAMOD) 0 -- select
event-counting mode 1 -- select gated
accumulation mode - bit 4 (PEDGE) its meaning
depends on bit 5
PAMOD PEDGE Action on clock
0 0 PAI falling edge
increments the PACNT counter 0 1
PAI rising edge increments the PACNT counter 1
0 A low on PAI pin inhibits
counting 1 1 A high on PAI
pin inhibits counting
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Example 8.14 Interrupt after N events. Events
are converted into signal edges and are connected
to the PAI pin. N is smaller than 255. Write a
program to interrupt the 68HC11 after N
event. Solution regbas equ 1000 TMSK2 equ
24 TFLG2 equ 25 PACTL equ 26 PACNT equ
27 PA_INI equ 50 value to enable PA, select
event-counting mode, falling edge active N equ
. event count org C000 ldx regbas bclr
TFLG2,X DF clear the PAOVF flag ldaa
N nega complement N staa PACNT,X
initialize PACNT to -N ldaa PA_INI staa
PACTL,X bset TMSK2,X 20 enable the PACNT
overflow interrupt cli enable interrupt to
the 68HC11 end