Huffman Encoder Project

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Huffman Encoder Project
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Huffman Encoder Project
Howd - Zur Hung Eric Lai Wei Jie Lee Yu - Chiang
Lee Design Manager Jonathan P. Lee
Overall Project ObjectiveDesign a Low Power
Huffman Encoder
Final Presentation April 30th, 2007
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Agenda of Presentation

• About Huffman Compression (Wei Jie)
• Marketing (Wei Jie)
• Project Description (Wei Jie)
• Design Methodology (Randal)
• Original Huffman Recipe (Randal)
• Our Huffman Encoder (Randal)
• Design Decisions (Randal)
• Behavioral/Algorithmic Description (Eric)
• Floorplan Evolution (Eric)
• Layout (John)
• Verification (Eric)
• Issues Encountered (John)
• Specifications (John)
• Conclusions (John)

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About Huffman

• Huffman is a compression algorithm
• Often used as a back-end to other
  compressions
• Greedy algorithm

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The Need for Compression

• It is becoming a wireless world
• Wireless bandwidth limited
• Power is limited
• COMPRESSION!
• Reduce data size Save power time bandwidth

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Why Huffman?

• Lossless
• Statistical
• David Huffman is the man!
• Outdid Shannon-Fano coding

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Project Description
Our Huffman Encoder is a fast and power
efficient solution to data compression with
on-chip cache
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Why Hardware?

• Hardware compression out performs software
  based solution
• Small, affordable, and power efficient chip
  is perfect for portable devices

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Hardware Huffman Solution

• Low power, compact, full-custom ASIC
• Saves power, time, and system resources
• Compress data packets on network cards
• Cell phones, PDA, Laptop

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Design Methodology

• Understand the algorithm
• Design functional blocks
• Behavioral Verilog
• Structural Verilog
• Schematic
• Layout
• Simulations

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Specifics of Huffman

• Procedure
• pre-scan data and count frequency
• iteratively find least two frequent word and
  build a tree
• encode word according to the final tree
  structure

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Our Huffman

• Procedure
• pre-scan data, count frequency, and assign
  unique group number
• iteratively find least two frequent word to
  update group number and encoding
• finish encoding look up table

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Design Decisions

• 5-bit input word size
• 16-bit frequency
• Two SRAMs
• Adders 16-bit Carry Select Adders
• Serial output
• Control logic to shut down modules

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Behavioral / Algorithm Description
turns off unused blocks to reduce power
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Schematic Diagram
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Floorplan Prelayout
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Floorplan Midlayout
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Final Chip Layout
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Top
countFreq
Find2Freq
Combine
SRAMfreqGroup
SRAMcodeLength
serial output
control
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CountFrequency
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Find2Freq
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Combine
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SerialOutput
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SRAM(FreqGroup)
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Poly
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Metal 1
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Metal 2
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Metal 3
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Metal 4
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Verification Verilog

• Matched Verilog results with MATLAB results
• Verified the successful compression of several
  test cases including parts of an image file

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Verification Schematic

• Vigorously tested each block
• Combined them and encoded several words

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Verification Layout

• Verified strong signal integrity
• Buffered high fan-outs and long wires
• Critical Path 4.88 ns
• All outputs of modules go through registers

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Component Specifications
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Final Specifications

• Number of Transistors 23,322
• Area 288.18 x 273.645 78859 µm2
• Density 0.296 (transistors/µm2)
• Aspect Ratio 11.05
• Pin Count 52 pins
• Input 5-bit data input, start, done, finish
• Output 36-bit treeOutput, treeReady, out,
  request, error
• vdd!, gnd!, clk, reset
• Final Clock Speed 200 MHz

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Final Specifications

• Final result is up to 1800 times faster than
  Java! (probably because its Java)
• Compressed 640 bits of an image
• Java results 10 ms
• Centrino 1.5 GHz
• 512 RAM
• Our hardware Huffman 5.4 us
• 1071 cycles

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Issues Encountered

• Bad estimate for original floorplan
• Long SRAM simulation time
• SRAM sense amp issue
• Too much poly!
• Cannot route through SRAM

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Conclusions

• Next Steps
• Scale up design
• Better compression ratio
• Higher throughput
• Meeting of the Minds
• HUFFMAN DECODER!!

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Questions?