Hardware JPEG Encoding of VGA Camera Images

1
Hardware JPEG Encoding of VGA Camera Images

• By Sean Gordoni
• Project Partner Toyon Research Corporation

2
Background

• Camera data transmission ITU 656
• JPEG Encoding (i.e. Motion JPEG)
• Microblaze soft-core processor
• Send camera sensor info over MIMO link

3
Block Diagram
Xilinx FPGA
Y
CMOS Camera with ITU 656 YUV 422 Output
ITU 656 Data Stream Decoder And FIFOs
JPEG Encoder
8-Bit Data Bus
Cr
Cb
Data Clock
FSL Channel
External Interface
MicroBlaze 32-Bit Soft-core Processor with OBD
Peripherals i.e. RS232,DRAM
4
VGA Camera

• The OV7660 is a low-voltage CMOS image sensor.
• Controlled through SCCB (Serial Camera Control
  Bus)
• Outputs 640x480 images at 30fps.
• Offers a variety of digital output format
  including ITU 656 progressive scan

5
Xilinx FPGA

• Development to be done on Virtex-4 evaluation
  board.
• Allows rapid prototyping and testing without the
  need to debug PCB design

6
ITU-656 Specification

• 27Mhz Syncronous digital interface
• Uses an 8-bit data bus and data clock
• Video is split into Chromanince and Luminance
• Start of Active Video and End of Active Video
  headers, 4-byte sequences, are used to denote
  start and end of line, as well as vertical
  blanking

V vs U with Y0.5
7
ITU 656 Decoder and Buffer

• Hand-Coded Verilog module that decodes ITU 656
  data stream and stores in a series of FIFOs to
  hold eight entire lines of video. Write enable
  signals for FIFOs are generated from SAV and EAV
  headers and a set of counters
• Output of each of the three components, YUV, is
  fed to first stage of JPEG Encoder in the form of
  an 8 pixel X 8 pixel macro-block

Macro-Block
8
JPEG Encoding

• Typically JPEG compression can result in over
  80 smaller file size, but JPEG compression is a
  lossy compression

9
DCT

• The Discrete Cosine Transform, similar to the
  Fast Fourier Transform (FFT), changes the pixel
  information into the frequency domain.
• In a small block there is likely not much high
  frequency information, this is the fundamental
  idea behind JPEG compression

10
Quantizer

• The Quantizer divides and rounds the DCT
  coefficient values, this is where information is
  lost
• Values are determined by a preset Quantizer
  Table, this table determines compression ratio
  and resulting image quality
• Typically high frequency values are set to 0
  because they are small and have high quantization
  coefficients

11
Huffman Encoder

• A lossless variable length entropy encoder
• Values that appear more often in the file are
  assigned smaller code length
• EX The 8-bit value 00000000 might be
  represented by 1111, resulting in a 50
  compression ratio for all values of 0
• A Huffman table is stored in the file to decode
  the values

12
MicroBlaze

• 32-bit soft-core RISC-based microprocessor
• Fast Simplex Link (FSL) will be used to
  communicate with JPEG encoder
• FSL is a Xilinx IP core that allows for fast
  uni-directional communication interface that
  easily integrates with the MicroBlaze core

13
Progress

• ITU 656 decoder and buffer module is near
  completion
• Currently test benching and debugging timing

14
Test Methodology

• Test Patterns are setup in data generator,
  currently only an 8-bit count is used and
  duplicated for each line
• Data checker knows what data to expect and
  compares it with incoming data, if there is a
  discrepancy an error is printed out to modelsim
  console

MODEL SIM TB
ITU-656 Data Generator to mimic CMOS camera
Data Checker to verify correctness of decoder
module
Y
ITU 656 Data Stream Decoder And FIFOs
8-Bit Data Bus
Cr
Cb
Data Clock
15
Future Work

• Complete ITU656 decoder module and add more test
  patterns to verify correctness and functionality
• Connect with DCT, Quantizer, then Huffman Encoder
  and test bench.
• Connect full JPEG encoder to MicroBlaze via FSL