De-synchronization: from synchronous to asynchronous

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De-synchronizationfrom synchronous to
asynchronous
Based on the paper Blunno, Cortadella,
Kondratyev, Lavagno, Lwin, Sotiriou, Handshake
protocols for de-synchronization, ASYNC 2004.
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Outline

• What is de-synchronization ?
• Behavioral equivalence
• 4-phase protocols for de-synchronization
• Concurrency
• Correctness
• An example

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Synchronous
CLK
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Synchronous circuit
L
L
L
L
0
0
1
1
CLK
0
0
L
L
5
De-synchronization
L
L
L
L
0
0
1
1
0
0
L
L
6
De-synchronization
Distributed controllers substitute the clock
network
C
C
C
C
C
C
The data path remains intact !
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Design flow

• Think synchronous
• Design synchronousone clock and edge-triggered
  flip-flops
• De-synchronize (automatically)
• Run it asynchronously

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Prior work

• Micropipelines (Sutherland, 1989)
• Local generation of clocks
• Varshavsky et al., 1995
• Kol and Ginosar, 1996
• Theseus Logic (Ligthart et al., 2000)
• Commercial HDL synthesis tools
• Direct translation and special registers
• Phased logic (Linder and Harden, 1996)
  (Reese, Thornton, Traver, 2003)
• Conceptually similar
• Different handshake protocol (2 phase vs. 4 phase)

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Automatic de-synchronization

• Devise an automatic method forde-synchronization
• Identify a subclass of synchronous circuits
  suitable for de-synchronization
• Formally prove correctness

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Outline

• What is de-synchronization ?
• Behavioral equivalence
• 4-phase protocols for de-synchronization
• Concurrency
• Correctness
• An example

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Synchronous flow
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De-synchronized flow
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Flow equivalence

• Guernic, Talpin, Lann, 2003

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A
B
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Flow equivalence
CLK
A 1 3 0 2 1
5 3 1 6 0
B 5 1 2 3 1
4 2 4 3 1
Synchronous behavior
A 1 3 0 2
1 5 3 1 6 0
B 5 1 2 3 1 4
2 4 3 1
De-synchronized behavior
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Flow equivalence
CLK
A 1 3 0 2 1
5 3 1 6 0
B 5 1 2 3 1
4 2 4 3 1
Synchronous behavior
A 1 3 0 2
1 5 3 1 6 0
B 5 1 2 3 1 4
2 4 3 1
De-synchronized behavior
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Outline

• What is de-synchronization ?
• Behavioral equivalence
• 4-phase protocols for de-synchronization
• Concurrency
• Correctness
• An example

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L
L
L
L
0
0
1
1
0
0
L
L
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C
C
C
C
C
C
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L
C
45
A
B
C
D
0
0
0
0
46
A
B
C
D
0
1
0
0
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A
B
C
D
0
0
0
0
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A
B
C
D
1
0
0
0
A latch cannot read another data item untilthe
successor has captured the current one
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A
B
C
D
0
0
0
0
50
A
B
C
D
0
0
0
1
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A
B
C
D
0
0
0
0
52
A
B
C
D
0
0
1
0
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A
B
C
D
0
1
1
0
A latch cannot become opaque before
havingcaptured the data item from its predecessor
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A
B
C
D
0
0
1
0
A latch cannot become opaque before
havingcaptured the data item from its predecessor
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A
B
C
D
0
0
0
0
A latch cannot become opaque before
havingcaptured the data item from its predecessor
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A
B
C
D
0
0
0
0
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A
B
C
D
A B C
D A- B-
C- D-
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Outline

• What is de-synchronization ?
• Behavioral equivalence
• 4-phase protocols for de-synchronization
• Concurrency
• Correctness
• An example

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Can we increase concurrency ?
not flow-equivalent
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Can we reduce concurrency ? How much ?
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(8 states)
(6 states)
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de-synchronization model
fully decoupled (Furber Day)
GasP, IPCMOS
semi-decoupled (Furber Day)
non-overlapping
simple 4-phase
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de-synchronization model
fully decoupled (Furber Day)
GasP, IPCMOS
simple 4-phase
non-overlapping
semi-decoupled (Furber Day)
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4-phase latch controllers
Lt
Lt
Rin
Rin
Rout
Rout
Aout
Ain
Ain
Aout
Furber and Day, IEEE Trans. VLSI, June
1996 Implementation note Lt0 (transparent),
Lt1 (opaque)
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4-phase latch controllers
Rin
Rout
Lt
Ain
Aout
?
Lt
Rin-
Rout-
Rin
Rout
Lt-
Aout
Ain
Ain-
Aout-
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4-phase latch controllers
Rin
Rout
Ain
Aout
Lt
Lt
Rin-
Rout-
Rin
Rout
Aout
Ain
Lt-
Ain-
Aout-
Simple 4-phase controller
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4-phase latch controllers
Rin
Rout
Ain
Aout
Lt
Rin-
Rout-
Lt-
Ain-
Aout-
Simple 4-phase controller
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4-phase latch controllers
Rin
Rout
A
Ain
Aout
Lt
Lt
Rin-
Rout-
A-
Rin
Rout
Aout
Ain
Ain-
Aout-
Lt-
Semi-decoupled controller
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4-phase latch controllers
Rin
Rout
A
Ain
Aout
Lt
Rin-
Rout-
A-
Ain-
Aout-
Lt-
Semi-decoupled controller
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4-phase latch controllers
Rin
Rout
A
Ain
Aout
Lt
B
Lt
Rin-
Rout-
A-
Rin
Rout
Aout
Ain
Ain-
Aout-
Lt-
B-
Fully decoupled controller
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4-phase latch controllers
Rin
Rout
A
Ain
Aout
Lt
B
Rin-
Rout-
A-
Ain-
Aout-
Lt-
B-
Fully decoupled controller
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4-phase latch controllers (state graphs)
Fully decoupled controller
Semi-decoupled controller
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A
B
Rx
Ri
Ro
cntrl
cntrl
Ax
Ai
Ao
Ri A- Rx
B- Ro Ai
Ax Ao
Ri- A Rx-
B Ro- Ai-
Ax- Ao-
(semi-decoupled 4-phase protocol)
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A
B
Rx
Ri
Ro
cntrl
cntrl
Ax
Ai
Ao
A-
B-

A
B

(semi-decoupled 4-phase protocol)
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A
B
Rx
Ri
Ro
cntrl
cntrl
Ax
Ai
Ao
A-
B-

A
B

(semi-decoupled 4-phase protocol)
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A
B
Rx
Ri
Ro
cntrl
cntrl
Ax
Ai
Ao
A-
B-

A
B

(semi-decoupled 4-phase protocol)
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A
B
Rx
Ri
Ro
cntrl
cntrl
Ax
Ai
Ao
A-
B-

A
B

(semi-decoupled 4-phase protocol)
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A
B
Rx
Ri
Ro
cntrl
cntrl
Ax
Ai
Ao
A-
B-

A
B

(semi-decoupled 4-phase protocol)
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A
B
Rx
Ri
Ro
cntrl
cntrl
Ax
Ai
Ao
A-
B-

A
B

(semi-decoupled 4-phase protocol)
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Outline

• What is de-synchronization ?
• Behavioral equivalence
• 4-phase protocols for de-synchronization
• Concurrency
• Correctness
• An example

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Which protocols are validfor de-synchronization ?
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Theorem the de-synchronization protocol
preserves flow-equivalence Proof by
induction on the length of the traces
Induction hypothesis same latch values at reset
Induction step same values at cycle i
? same values at cycle i1
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Theorem any reduction in concurrency
preserves flow-equivalence
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Any hybrid approach preserves flow-equivalence !
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A
B
C
D
A B C
D A- B-
C- D-
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A
B
C
D
A B C
D A- B-
C- D-
semi-decoupled
non-overlapping
fullydecoupled
Flow-equivalence is preserved, but
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Liveness

• Preservation of flow-equivalenceall the
  generated traces are equivalent
• Are all traces generated ?(Is the marked graph
  live ?)Not always !

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A B C
D A- B-
C- D-
Semi-decoupled 4-phase handshake protocol
Liveness all cycles have at least one token
Commoner 1971
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A B C
D A- B-
C- D-
Simple 4-phase handshake protocol
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Results about liveness

• At least three latches in a ring are required
  with only one data token circulatingMuller
  1962
• Theorem (this paper)any hybrid combination of
  protocols is live if the simple 4-phase protocol
  is not usedProof any cycle has at least one
  token

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Valid for de-synchronization
de-synchronization model
fully decoupled (Furber Day)
GasP, IPCMOS
simple 4-phase
non-overlapping
semi-decoupled (Furber Day)
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Outline

• What is de-synchronization ?
• Behavioral equivalence
• 4-phase protocols for de-synchronization
• Concurrency
• Correctness
• An example

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Async DLX block diagram
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Synchronous RTL
Synchronous
Desynchronized

Cycle 4.4ns Power 70.9mW Area 372,656?m
Cycle 4.45ns Power 71.2mW Area 378,058?m

• All numbers are after Placement Routing
• Total of 1500 flip-flops, 3000 latches
• DE-SYNC design includes 5 controllers, each
  driving 2 clock trees
• Power numbers include the clock tree
• Technology UCM/Virtual Silicon 0.18 µm

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Discussion

• The de-synchronization model provides an
  abstraction of the timing behavior

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• Timing analysis
• Exploration of the design space

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Conclusions

• EDA tools require a formal support(they must
  work for all circuits)
• A complete characterization of 4-phase protocols
  has been presented(partial order based on
  concurrency)
• Design flow developed at Cadence Berkeley Labs
• Automated from gate netlist
• Static timing analysis to derive matched delays
• Constrained PR to meet timing constraints