High Bandwidth and High Gain Rail to Rail Amplifier

1
High Bandwidth and High Gain Rail to Rail
Amplifier

-

• Chenlu Hou
• Chih-hao Kuo
• Thompson Wei Cheng Lin

2
Outline

• OpAmp Design Specifications
• Implementation
• Input stage (complementary pairs)
• Gain Stage (cascode)
• Output Stage (source follower)
• Complete Circuit Schematic
• Simulation Results
• Reference
• Conclusion

3
Op-Amp Design Specifications

• Rail to rail common mode input Vss to Vdd(2.5V)
• Low frequency gain 70 dB
• Unity gain bandwidth 100 MHz
• Phase margin of 65 degree
• 0.25 um CMOS technology
• Robust to load variation

4
Implementation - Input Stage
PMOS differential input
NMOS differential input
5
Input Stage Complementary Differential Pairs
Intermediate Vcm
Choose
6
Input Stage Complementary Differential Pairs

I4Iref
N-channel switch open P-channel switch close
N-channel switch close P-channel switch open
7
Common Gate Amp
Vdd

• Double cascoded configureation
• Isolate output resistance from complementary
  input pairs
• Large gain and small parasitc capacitance
• Want dominant pole as large as possible
• Large W/L ratio (large gain) small W (large BW)

Vb1
from NMOS differential inputs
Vb2
Vb3
from PMOS differential inputs
Vss
8
Output Stage Source Follower
Vdd

• Vout tracks Vin
• Large Cp (2p) low frequency pole
• Adding shunt resistances to enlarge pole
  frequency
• DC offset
• Large gm of SF and small I

Vin
Vb
9
Complete Circuit Schematic
Complementary Input Stage
Common Gate Amp
Source Follower
Biasing Stage
10
Simulation Result Gain, Unity Gain Frequency,
and Phase Margin
Low Frequency Gain gt70.7dB
Vdd2.5V T27o CL2pF
Unity Gain Frequency gt 86MHz
Phase at ?u 115.5o gt Phase Margin 64.5o
11
Simulation Result Temperature variation T 85C
Low Frequency Gain gt 68 dB
Unity Gain Frequency gt 75MHz
Phase at at ?u 114.6o gt Phase Margin 65.4o
12
Simulation Result Output Swing and Output offset
Output Swing gt 1 V
Output Offset 67 µV
13
Layout (50u x 100u)
Common Gate amp
Biasing Circuits
Source Follower
Complementary Input Stage
14
Specifications of the designed Op-Amp
15
References

• A High Bandwidth Constant gm and Slew Rate Rail
  to Rail CMOS Input Circuit and its application to
  Analog Cells for Low Voltage VLSI systems by
  William Redman-White
• Operational Amplifiers Rail to Rail Input Stages
  Using Complementary Differential Pairs by Ahmed
  Gharbiya
• A Compact Power Efficient 3 V CMOS Rail-to-Rail
  Input/Output Operational Amplifier for VLSI cell
  Libraries by Ron. Hongervorst, John P. Tero,
  Ruud G. H. Eschauzier, and Johan H. Huijsing
• Robust Design of Rail-to-Rail CMOS operational
  Amplifiers for a Low Power Supply Voltage by
  Satoshi Sakurai and Mohammed Ismail
• Constant-gm Rail-to-Rail CMOS Op-Amp Input Stage
  with Overlapped Transition Regions by Mingsheng
  Wang, Terry L. Mayhung, Jr, Sherif H. K. Embabi
  and Edgar Sanchez-Sinencio
• Lecture notes on Constant Gm Rail-to-Rail Input
  Stage by Dr. Howard Luong
• Lecture notes on Rail-to-Rail Op Amps by Edgar
  Sanchez-Sinencio

16
Conclusion

• Our design met all the design constraints in most
  cases
• Rail to rail common mode input
• High gain and unity gain bandwidth
• Questions