Lava

1
Lava

• Mary Sheeran, Koen Claessen
• Chalmers University of Technology
• Satnam Singh, Xilinx

2
Lava

• Not so much a hardware description language
• More a style of circuit description
• Emphasises connection patterns
• Think of Lego

3
Behaviour and Structure
g
f
f -gt- g
4
Parallel Connection Patterns
f -- g
5
map f
6
Four Sided Tiles
7
Column
8
Full Adder in Xilinx Lava
cout
b
sum
a
cin
fa (cin, (a,b)) (sum, cout)
where part_sum
xor (a, b) sum xorcy
(part_sum, cin) cout
muxcy (part_sum, (a, cin))
9
Generic Adder
adder col fa
10
Top Level
adder16Circuit do a lt- inputVec a
(bit_vector 15 downto 0) b lt- inputVec
b (bit_vector 15 downto 0) (s, carry)
lt- adder1 (a, b) sum lt- outputVec sum
(scarry)
(bit_vector 16 downto 0) ? circuit2VHDL add16
adder16Circuit ? circuit2EDIF add16
adder16Circuit ? circuit2Verilog add16
adder16Circuit
11
114 Lines of VHDL
library ieee use ieee.std_logic_1164.all
entity add16 is port(a in std_logic_vector
(15 downto 0) b in std_logic_vector
(15 downto 0) c out std_logic_vector
(16 downto 0) ) end entity add16
library ieee, unisim use ieee.std_logic_1164.
all use unisim.vcomponents.all architecture
lava of add16 is signal lava
std_logic_vector (0 to 80) begin ... lut2_48
lut2 generic map (init gt "0110") port map (i0 gt
lava(5), i1 gt lava(21), o gt lava(48))
xorcy_49 xorcy port map (li gt lava(48), ci gt
lava(47), o gt lava(49)) muxcy_50 muxcy
port map (di gt lava(5), ci gt lava(47), s gt
lava(48), o gt lava(50)) lut2_51 lut2
generic map (init gt "0110") port map (i0 gt
lava(6), i1 gt lava(22), o gt lava(51))
xorcy_52 xorcy port map (li gt lava(51), ci gt
lava(50), o gt lava(52)) muxcy_53 muxcy
port map (di gt lava(6), ci gt lava(50), s gt
lava(51), o gt lava(53)) lut2_54 lut2
generic map (init gt "0110") port map (i0 gt
lava(7), i1 gt lava(23), o gt lava(54)) ...
12
EDIF...
(edif add16 (edifVersion 2 0 0) (edifLevel 0)
(keywordMap (keywordLevel 0)) (status (written
(timeStamp 2000 11 19 15 39 43) (program
"Lava" (Version "2000.14")) (dataOrigin
"Xilinx-Lava") (author "Xilinx Inc.") ) ) ...
(instance lut2_78 (viewRef prim
(cellRef lut2 (libraryRef lava_virtex_lib))
) (property INIT (string "6"))
(property RLOC (string "R-7C0.S1"))
) (net lava_bit38 (joined
(portRef o (instanceRef muxcy_38))
(portRef ci (instanceRef muxcy_41))
(portRef ci (instanceRef xorcy_40)) )
)
13
Xilinx FPGA Implementation

• 16-bit implementation on a XCV300 FPGA
• Vertical layout required to exploit fast carry
  chain
• No need to specify coordinates in HDL code

14
16-bit Adder Layout
15
Four adder trees
16
No Layout Information
17
Full Adder in Chalmers Lava
fa (cin, (a,b)) (sum, cout)
where part_sum
xor2 (a, b) sum xor2
(part_sum, cin) cout
mux (part_sum, (a, cin))
18
import Lava fa (cin,(a,b)) (sum,cout)
where part_sum xor2(a,b) sum
xor2(part_sum,cin) cout
mux(part_sum,(a,cin)) Maingt simulate fa
(high,(high,high)) (high,high)
19
import Lava import Patterns fa (cin,(a,b))
(sum,cout) where part_sum xor2(a,b)
sum xor2(part_sum,cin) cout
mux(part_sum,(a,cin)) add row fa Maingt
simulate add (low,(low,high),(high,low),(low,high
)) (high,high,high,low)

20
import Lava import Arithmetic fa (cin,(a,b))
(sum,cout) where checkFullAdd ins ok
where out1 fa ins out2 fullAdd ins
-- Lava built-in fullAdder ok out1 ltgt
out2 Maingt vis checkFullAdd Vis ... (t0.7)
Valid.

21
In file Verify/circuit.mv

.model circuit.inputs i0.inputs i1.inputs
i2.outputs good.table -gt low0.latch low
initt.reset initt1.table -gt w21.table i0 -gt
w90 01 1.table i1 -gt w100 01 1.table w9 w10
-gt w80 0 00 1 11 0 11 1 0
.. .table initt w2 w1_x -gt w1 1 - - w2 0 - -
w1_x .table w1 -gt good 0 0 1 1 .end
22
import Lava import Arithmetic fa (cin,(a,b))
(sum,cout) where checkFullAdd ins ok
where out1 fa ins out2 fullAdd ins
-- Lava built-in fullAdder ok out1 ltgt
out2 Maingt satzoo checkFullAdd Vis ... (t0.1)
Valid.

23
In file Verify/circuit.cnf In
file Verify/circuit.cnf.out

c Generated by Lava2000 c c i0 6 c i1 7 c i2
8 p cnf 21 57 -5 6 7 0 -5 -6 -7 0 5 -6 7 0 5 -7
6 0 -4 5 8 0 -4 -5 -8 0 4 -5 8 0 4 -8 5 0
Parsing DIMACS Solving (randomize) 10000/38
(0.00 ). Computing static variable
order. restarts 0 conflicts
10 learnt_clauses
5 forgotten_clauses 3 decisions
10 propagations 79 inspect_binary
49 inspect_normal
194 inspect_learnt 2 CPU time
0 s UNSATISFIABLE real 0.1 user
0.0 sys 0.0
.. 11 -12 -21 0 -11 12 0 -11 21 0 1 -2 -11 0 -1
2 0 -1 11 0 -1 0
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Equivalence Checking
25
View as property checking
26
Synchronous Observer

• Only one language (so easier to use)
• Safety properties
• Used in verification of control programs

27
Different styles
deland (a,b) c where newa delay low a
newb delay low b c and2(newa,newb) del
and1 (delay low -- delay low) -gt-
and2 deland2 delay (low,low) -gt- and2 deland3
delay zero -gt- and2
28
Simulating sequential circuits
Maingt simulateSeq deland (low,low),(high,low),(hi
gh,high),(low,low) low,low,low,high Maingt
simulateSeq deland2 (low,low),(high,low),(high,hi
gh),(low,low) low,low,low,high
29
Checking equivalence
anddel and2 -gt- delay low prop_Equivalent
circ1 circ2 a ok where out1 circ1 a
out2 circ2 a ok out1 ltgt out2 Maingt vis
(prop_Equivalent deland anddel) Vis ... (t0.2)
Valid. Maingt smv (prop_Equivalent deland3
anddel) Smv ... (t0.4) Valid.
30
In Verify/circuit.smv
DEFINE w5 0 DEFINE w6 i0 ASSIGN init(w4)
w5 ASSIGN next(w4) w6 DEFINE w8
i1 ASSIGN init(w7) w5 ASSIGN next(w7)
w8 DEFINE w3 w4 w7 DEFINE w10 w6
w8 ASSIGN init(w9) w5 ASSIGN next(w9)
w10 DEFINE w2 !(w3 lt-gt w9) DEFINE w1
!(w2) SPEC AG w1
-- Generated by Lava2000 MODULE main VAR w1
boolean VAR w2 boolean VAR w3 boolean VAR
w4 boolean VAR w5 boolean VAR w6
boolean VAR i0 boolean VAR w7 boolean VAR
w8 boolean VAR i1 boolean VAR w9
boolean VAR w10 boolean
31
Many delays
delayN 0 init id delayN n init delay init -gt-
delayN (n-1) init dAnd n delayN n (low,low)
-gt- and2 andD n and2 -gt- delayN n low Maingt
smv (prop_Equivalent (dAnd 10) (andD 10)) Smv
... (t0.9) Valid. Maingt smv (prop_Equivalent
(dAnd 15) (andD 15)) Smv ... (t230.3)
Valid. Same verification for 20 takes more than
35 minutes
32
Note

• Could be viewed as Lustre (or similar) embedded
  in Haskell
• Generic circuits and connection patterns easy to
  describe (the power of Haskell)
• Verify FIXED SIZE circuits (squeezing the
  problem down into an easy enough one)

33
Working on lists
G
F
parl F G halveList -gt- (F -- G) -gt- append
34
two f
f
f
35
two (two f)
36
Many twos
twoN 0 circ circ twoN n circ two (twoN
(n-1) circ)
37
Interleave
f
f
ilv f unriffle -gt- two f -gt- riffle
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Many interleaves
ilv (ilv (ilv C))
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Many interleaves
ilvN 0 circ circ ilvN n circ ilv (ilvN
(n-1) circ)
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Wiring
id2
swap
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Butterfly
bfly circ
bfly circ
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Defining Butterfly
bfly 0 circ id bfly n circ ilvN (n-1)
circ -gt- two (bfly (n-1) circ)
43
Butterfly Layout on an FPGA
44
Bitonic merger
compInt x,y imin(x,y), imax(x,y) compBit
x,y and2(x,y), or2(x,y) Maingt simulate
(bfly 3 compInt) 1,3,5,7,8,6,4,2 1,2,3,4,5,6,7,
8 Maingt simulate (bfly 2 compBit)
low,high,low,high low,high,low,high
45
Describe connection pattern

• Then plug in variety of components, including
  bit-serial etc. (see work of Vuillemin)
• Sorters and mergers verified using 0-1 principle
  and SAT-solver (see Knuth vol. 3)
• Used higher order functions and polymorphism

46

Reduction tree for multiplier
5
4
4

3
3
carries
2
Fast Adder
47

• multiply (as,bs) p1ss
• where
• (p1p2,p3ps) prods_by_weight (as,bs)
• is redArray ps
• ss binaryAdder
  (p2,p3is)
• redArray addEmpty -gt- row compress -gt- first

48
compress

49
other cases

insC
h-cell
50

carries
5
4
3
51
possible f-cell

fullAdd
halfAdd cells similar. Gives shortest wires
multiplier. Not great!
52
But we just need to vary these!
insC

fullAdd
insS
53
Dadda

fullAdd
excellent multiplier, but famous for
incomprehensibility, irregularity
54
Regular reduction tree (Eriksson et al, CE)

fullAdd
Nowhere near as good as Dadda, but inspired this
work
55
Idea Harden the wiring during circuit generation
using clever circuits. Shadow values estimate
delay through wires and cells.

cleverInsert
fullAdd
fullAdd
iddown
cleverInsert
56

• cleverInsert row cswap -gt- apr
• forms necessary wiring based on context (delays
  on shadow wires)

57

Structure of circuit description (generator)
remains unchanged

• redArrayD hAdd fAdd iddown hds fds d ps
• ((redArrayW
• (combine hAdd (halfAddDelI hds))
• (combine fAdd (fullAddDelI fds))
• (combine iddown (iddownDelI d))
• cleverInsert
• cleverInsert) -gt- unmark) (mark ps)
• combine c a unzipp -gt- par c a -gt- zipp

58
User explores designs by writing small analysis
functions and playing

• Maingt daddatest 16
• 0,20,8,45,40,50,45,70,65,75,70,90,85,
  95,90,100,95,115,110,120,
• 115,120,115,125,120,125,120,140,135,145,
  140,145,140,145,140,140,
• 135,135,130,130,125,125,120,120,115,115,
  110,110,105,105,100,90,
• 85,85,80,45,0,40
• Maingt simulate (compareW (daddatestW 16)
  (daddatest 16))
• 0,0,2,0,2,0,2,2,4,2,4,4,6,6,8,6,8
  ,8,10,8,10,12,14,12,14,12,
• 14,16,18,16,18,16,18,16,18,18,20,20,2
  2,22,24,22,24,8,10,10,
• 12,12,14,12,14,6,8,6,8,0,0,0
• Maingt satzoo (prop_mult multTDMW 8)
• Satzoo ... (t308.8) Valid.

59
Result

• Simple parameterised description of fast adaptive
  multiplier. Promises to perform well.
• Like TDM except that wire-length, and not only
  gate-delay is taken into account in choosing
  which connections to make. Description is very
  similar to that of basic multiplier.
• All done inside Lava. Next step, go the whole
  hog.

60
Current uses of Lava

• All at low level of design
• Teaching and research in formal verification at
  Chalmers
• FPGA cores at Xilinx
• Our research on Wired builds upon Lava

61
Summary

• Circuit generators are short and sweet
• Formal verification of fixed size circuits
• Clever circuits a good idiom
• Simple wire and gate delay modelling components
  can guide synthesis (could be made fancier,
  collaboration needed)
• Design exploration uses Haskell as scripting
  language (an unexpected bonus)
• Need links to lower level tools
• Concentration on datapaths