EEGNCSCI 660 Introduction to VLSI Design Lecture 7

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EEGN-CSCI 660 Introduction to VLSI
DesignLecture 7

• Khurram Kazi

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Behavioral Modeling with Verilog

• Verilog allows design functionality in an
  algorithmic manner i.e. describe the behavior of
  the model.
• Design at this level resembles C programming more
  than it resembles digital circuit design.
• Verilog is rich in behavioral construct

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Topics under Behavioral Modeling

• Structured procedures always and initial
• Define blocking and nonblocking procedural
  assignments
• Delay based timing control mechanism in
  behavioral modeling
• Event based timing control mechanism in
  behavioral modeling
• Use the level-sensitive timing control mechanism
  in behavioral modeling
• Conditional statements using if and else
• Multiway branching, using case, casex and casx
  statements

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Topics under Behavioral Modeling

• Looping statements such as while, for, repeat and
  forever
• Define sequential and parallel blocks
• Some examples

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Structured procedures always and initial Review

• All statements inside an initial statement
  constitute an initial block
• Initial block starts at time 0
• Executes only once during a simulation
• If there are multiple initial blocks, each block
  starts to execute concurrently at time 0
• Each block finishes execution independently of
  the other blocks
• Multiple behavioral statements must be grouped,
  typically using begin and end.

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Structured procedures always and initial Review

• All statements inside an always statement
  constitute an always block
• always block starts at time 0
• Executes the statements continuously in a looping
  fashion
• This statement is typically used to model a block
  of activity that is repeated continuously in a
  digital circuit

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Procedural assignments

• Procedural assignments update values of reg,
  integer, real or time variables
• The values placed on a variable will remain
  unchanged until another procedural assignment
  updates the variable with another value

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Blocking assignments

• Blocking assignments are executed in the order
  they are specified in a sequential block
• A blocking assignment will not block execution of
  statements that follow in a parallel block
• The operator is used to specify blocking
  assignments

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Blocking assignments

• reg x, y, z
• reg 150 reg_a, reg_b
• integer count
• //All behavioral statements must be inside an
  initial or always block
• initial
• begin
• x 0 y 1 z 1 //scalar assignments
• count 0 //Assignment to integer variables
• reg_a 16b0 reg_b reg_a //initialize
  vectors
• 15 reg_a2 1b1 //bit select assignment with
  delay
• 10 reg_b1513 x, y, z //assign result of
  concatenation to part of a vector
• // variable within these braces are
  concatenated
• count count 1 // assignment to an integer
  (increment)
• end

Executed at time 0 Executed at time
15 Executed at time 25
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Nonblocking assignments

• Nonblocking assignments allow scheduling of
  assignments without blocking execution of the
  statements that follow in a sequential block.
• A lt operator is used to specify nonblocking
  assignments

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Nonblocking assignments affects on the code
// describing the differences between blocking
and non-blocking operator // "" blocking and
"lt" non-blocking operator initial
begin x 0 y 1 z 1 counter
0 reg_a lt 16'b0 reg_a lt reg_b reg_a2
lt 15 1'b1 //this value changes _at_ time 15
reg_b1513 lt 10 x, y, z //this value
changes _at_ time 10 // i.e. changes
before reg_a counter lt counter 1 //this
value changes _at_ time 0 end
endmodule concatenation operator values
within the curly braces are concatenated

• module blocking
• reg clk, reset, enable
• reg x, y, z
• reg 150 reg_a, reg_b
• integer counter
• initial
• begin
• reset 1'b0
• enable 1'b0
• 25 reset 1'b1
• 40 enable 1'b1
• end
• initial
• begin
• clk 0
• forever 10 clk !clk
• end

Simulator schedules a nonblocking assignment
statement to execute and continues to the next
statement in the block without waiting for the
nonblocking statement to complete execution
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Blocking vs non Blocking

• The difference between the two is that one is
  similar to variable in VHDL and the other acts
  like a signal
• Blocking in synonymous to
• assignment (more like a variable)
• Where as non blocking is represented by
• lt assignment (more like a signal)

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Non blocking assignment Non blocking infers two
flip flop after synthesis (when clock is in the
sensitivity list)

• module SimpleFlipFlop (clk, a, b, c)
• //Input ports
• input clk
• input a
• //Output ports
• output b, c
• reg b, c
• //Input ports data type
• //By rule all the input ports should be wires
• wire clk, a
• always _at_(posedge clk)
• begin
• b lt a
• c lt b
• end
• endmodule

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blocking assignment blocking statement infers
one flip flop in synthesis all the time (code
dependent)
module SimpleFlipFlop_blocking (clk, a, b,
c) //Input ports input clk input
a //Output ports output b, c reg b,
c //Input ports data type //By rule all the
input ports should be wires wire clk,
a always _at_(posedge clk) begin b a c
b end endmodule
Not a good way of inferring a flip flop
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Why at times blocking assignment is preferred

• At times some designers prefer blocking as they
  can see sharing of resources more
• readily
• reg 150 a, b, c, d, e, f, g, h
• reg 160 x, y, z
• always _at_ (posedge clk)
• begin
• x a b c d e f
• y x g
• z x h
• end
• reg 150 a, b, c, d, e, f, g, h // In this
  example resource sharing is synthesizer
• reg 160 y, z //
  dependant
• always _at_ (posedge clk)
• begin
• y lt (a b c d e f) g
• z lt (a b c d e f) h
• end

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Why at times blocking assignment is not desired

• Blocking statement can cause race condition
• file first.v
• module first (a, b, clk)
• input b, clk
• output a
• always _at_ (posedge clk)
• begin
• a b
• end
• file second.v
• module first ( b, c, clk)
• input c, clk
• output b
• always _at_ (posedge clk)
• begin
• b c
• end

Some simulators may evaluate module
second.v and then module first. This effectively
transfers contents of c to a in ONE clock cycle.
This is known as simulator race condition.
While some other simulators will execute module
first followed by second. Hence two
different simulation results AVOID USING
BLOCKING STATEMENT
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Inferring Latches

• module latches (y1, y2, y3, enable, a1, preset1,
  a2, preset2, a3, preset3)
• output y1, y2, y3
• input a1, preset1
• input a2, preset2
• input a3, preset3
• input enable
• reg y1, y2, y3

always _at_ (a1 or a2 or a3 or preset1 or preset2
or preset3 or enable) begin if (preset1)
y1 lt 1b1 else if (enable) y1 lt
a1 if (preset2) y2 lt 1b0 else
if (enable) y2 lt a2 if (preset3)
y3 lt 1b1 else if (enable) y3 lt
a3 end endmodule
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Golden Rule

• Golden Rule 1 To synthesize combinational logic
  using an always block, all inputs to the design
  must appear in the sensitivity list.
• http//www.doulos.com/knowhow/verilog_designers_gu
  ide/if_statement/
• Good website that gives simple Verilog examples

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Inferring counters
always _at_ (posedge clk) begin if (clear) //
Sync clear counter y3 lt 0 else
y3 lt y3 1 end always _at_ (posedge clk)
begin if (up_down) // up down counter
direction lt 1 else direction lt -1
y4 y4 direction // NOTICE HERE
// y4 assignment is outside the
if else end endmodule WOULD THIS CODE
GENERATE DANGLING/ UNCONNECTED WIRES OR PORTS???

• module counters (y1, y2, y3, y4, y5, y6, d, clk,
  enable, clear, load, up_down)
• output 70 y1, y2, y3, y4, y5, y6
• input 70 d
• input clk, enable, clear, load, up_load
• reg 70 y1, y2, y3, y4, y5, y6
• integer direction
• always _at_ (posedge clk)
• begin
• if (enable) // enable counter
• y1 lt y1 1
• end
• always _at_ (posedge clk)
• begin
• if (load) // loadable counter
• y2 lt d
• else
• y2 lt y2 1
• end

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Frequency Divider
always _at_ (posedge clk or negedge reset_n)
begin if (!reset_n) div11 lt 0
else if (counter 10) div11 lt 1
else div11 lt 0 end

• module div11 (clkdiv11, clk, reset_n)
• output clkdiv11
• input clk, reset_n
• reg div11
• reg 30 counter
• always _at_ (posedge clk or negedge reset_n)
• begin
• if (!reset_n)
• counter lt 0
• else if (counter 10)
• counter lt 0
• else
• counter lt counter 1
• end

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Some simple ALU functions
always _at_ (a or b or opcode) begin case
(opcode) addab f lt a b //add
inca f lt a 1 //increment a incb f lt
b 1 //increment b andab f lt a b
//a and b orab f lt a b // a or b
nega f lt !a //negation of a shal f
lt a ltlt 1 //shift a left shar f lt a
gtgt 1 //shift a right passa f lt a
//pass a as is passb f lt b //pass b as
is default f lt 8bx defautl output
endcase end endmodule

• module alu (f, a, b, opcode)
• parameter addab 4b0000,
• inca 4b0001, incb 4b0010, andab
  4b0011, orab 4b0100, nega 4b0101, shal
  4b0110,
• shar 4b0111, passa 4b1000, passb
  4b1001
• output 70 f
• input 70 a, b
• input 30 opcode
• reg 70 f

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FSM with four states
else begin next_state lt st_three
lsb lt 1 msb lt 1 end st_one if (up_down
0) begin next_state lt st_two
lsb lt 0 msb lt 1 end else
begin next_state lt st_zero lsb lt
0 msb lt 0 end

• module state_machine (lsb, msb, up_down, clk,
  reset_n)
• output lsb, msb
• input up_down, clk, reset_n
• parameter 10 st_zero 2b00,
• st_one 2b01, st_two 2b10,
• st_three 2b11
• reg lsb, msb
• reg present_state, next state
• always _at_ (up_down or present_state)
• // combinatorial part
• begin
• case (present_state) //0 up, 1 down
• st_zero if (up_down 0)
• begin
• next_state lt st_one
• lsb lt 1
• msb lt 0
• end

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FSM with four states contd

• st_two if (up_down 0)
• begin
• next_state lt st_three
• lsb lt 1
• msb lt 1
• end
• else
• begin
• next_state lt st_one
• lsb lt 1
• msb lt 0
• end
• st_three if (up_down 0)
• begin
• next_state lt st_zero
• lsb lt 0
• msb lt 0
• end

else begin next_state lt st_two
lsb lt 0 msb lt 1 end endcase end alw
ays _at_ (posedge clk or negedge reset_n)
//sequential part begin if (!reset_n)
present_state lt st_zero else
present_state lt next_state end endmodule
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While Loop example

• module While_example
• define TRU 1'b1
• define FALSE 1'b0
• reg 150 flag
• integer i //integer to keep the count in "flag"
• reg continue
• integer count
• initial
• begin
• count 0
• while (count lt 128) // Execute loop till count
  is 27
• //Exit loop at count of 128
• begin
• display ("Count d", count)
• count count 1
• end
• end

initial begin flag 16'b 0010_0000_0000_0000
i 0 continue TRU while ((i lt 16)
continue) //Multiple conditions using
operators begin if (flagi) begin
display ("Encountered a TRUE bit at element
number d", i) continue FALSE end
i i 1 end end endmodule