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RD on silicon pixels and strips

• Giuliana Rizzo
• for the Pisa BaBar Group

SuperB WorkShop Frascati-17 November 2006
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CMOS MAPS

• Principle of Operation
• Electrons generated by the incident particle in
  the undepleted epitaxial layer move by thermal
  diffusion.
• Q 80 e-h/?m -gt Signal 1000 e-
• Signal collected by the n-well/p-epi diode

Developed for imaging applications, recently
proven to work well also for charged particles.

• Advantages
• Same substrate for detector-readout
• less material in the detection region (thin down
  to 50 um)
• Sensor faster and more rad hard than CCDs
• CMOS deep submicron process
• low power consumption and fabrication costs
• electronics intrinsically radiation hard

• Lots of MAPS RD in many places with a
  conventional approach
• Charge-to-voltage conversion provided by sensor
  capacitance
• -gt small collecting electrode
• -gt small single pixel signal
• Extremely simple in-pixel readout configuration
  (3 NMOSFETs)
• -gt sequential readout
• -gt readout speed limitation

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A new approach for CMOS MAPS

• Use of commercial triple-well CMOS process to
  address the two previous limitations of
  conventional MAPS
• increase collecting electrode size
• increase the complexity of the in-pixel readout
  electronics

In triple-well processes a deep n-well is used to
provide N-channel MOSFETs with better insulation
from digital signals

• This feature exploited for a new approach in the
  design of CMOS pixels
• The deep n-well can be used as the collecting
  electrode
• A full signal processing circuit can be
  implemented at the pixel level overlaying NMOS
  transistors on the collecting electrode area

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Triple well CMOS MAPS
Standard processing chain for capacitive detector
implemented at pixel level
PRE
SHAPER
DISC
LATCH

• Charge preamplifier used for Q-V conversion
• Gain is independent of the sensor capacitance -gt
  collecting electrode can be extended to increase
  the signal
• RC-CR shaper with programmable peaking time (0.5,
  1 and 2 ?s)
• A threshold discriminator is used to drive a NOR
  latch featuring an external reset

• Fill factor deep n-well/total n-well area ?
  0.85 in the prototype test structures

Readout scheme compatible with existent
architectures for data sparsification at the
pixel level -gt improve readout speed
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First Results

• Prototype chip, with single pixels, realized in
  0.13 mm triple well CMOS process
  (STMicrolectronics)
• Very encouraging results
• Prove the principle
• Good agreements between measurements and
  simulation
• S/N 10 measured with electrons from 90Sr b
  source
• Pixel noise still high
• ENC 125 e- for known reason

• Second version of the chip currently under test
• Small pixel matrix (8x8, 50x50 mm2 ) with simple
  sequential readout.
• Improved noise performance pixel noise ENC 50
  e-
• Expected S/N 25

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RD Project

• Aim of our research program is to fabricate MAPS
  sensors, based on triple well commercial CMOS
  process, and develop the technology for the
  fabrication of thin silicon strip detectors.

• Final goal is to build a prototype of a thin
  silicon tracker (MAPS and thin silicon strip
  modules) with LV1 trigger capabilities (based on
  Associative Memories)
• Already working on the design of the readout
  architecture for MAPS matrix, with data
  sparsification at the pixel level, having in mind
  a Linear SuperB as target application.
• Technology for thin silicon strips on a large
  area is not well established. We will explore two
  alternatives epitaxial grown substrate and
  locally thinned high resistivity substrate.
• Important aspect of the project is to develop
  light mechanical and cooling structures for thin
  silicon modules to benefit of the very low
  material budget of the sensor itself.
• Test of the prototype tracker in a test beam in
  2008

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SLIM Collaboration

• This RD project will be pursued in the next 3
  years within the new SLIM (Silicon detectors with
  Low Interaction with Material) Collaboration,
  supported by the INFN and the Italian Ministry
  for Education, University and Research.
• The SLIM Collaboration is organized in 4 Work
  Packages to cover the various aspects of the
  project
• WP1 MAPS and Front End Electronics
• WP2 Thin silicon strips
• WP3 Trigger/DAQ
• WP4 Integration, Mechanics and Test Beam
• We have a quite detailed project plan
• Several Italian Institutes involved in the
  project
• Pisa (coordination), Pavia, Bergamo,Trieste,
  Torino, Trento, Bologna
• Total Manpower involved 12 FTE

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Backup
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Device Simulation (ISE-TCAD)

• Detailed physical simulations performed using
  ISE-TCAD software to
• understand the charge collection mechanism and
  its time properties
• study influence of neighboring pixel and n-wells
• optimize sensor design (needs 3D simulation, in
  progress)

• Preliminary results
• Collected charge 1500 e-
• assuming pepi thickness ? 15 ?m likely to be
  true.
• Charge collection drops rapidly out of deep nwell
  area
• Collection time 50 ns

Uncertainties about process Test structure
chip realized to measure some process parameters
-gt a crucial input for simulation
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Test Chip Layout
0.13 mm CMOS HCMOS9GP by STMicroelectronics
epitaxial, triple well process (available through
CMP, Circuits Multi-Projets)
channel 5 - pixel with input pad for charge
injection (830 mm2 collecting electrode area)
channel 1-2-5 have integrated injection
capacitance for readout electronics
characterization
Single devices
channel 6 - pixel with small (830 mm2) collecting
electrode area
channel 4 - pixel with large (2670 mm2)
collecting electrode area
channel 3- pixel with medium (1730 mm2)
collecting electrode area
channel 2 - pixel with input pad for charge
injection (100 fF detector simulating
capacitance)
channel 1 - pixel with input pad for charge
injection
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Gain Noise Measurements

• Charge sensitivity and Equivalent Noise Charge
  measured in the three channels with integrated
  injection capacitance Cinj
• Good agreement (10) with the post layout
  simulation results (PLS)

Gain440 mV/fC
ENC 11e- 425e- /pF

• Equivalent Noise Charge is linear with
  CTCDCFCinjCin (CDdetector
  capacitance, CFpreamplifier feedback
  capacitance, Cinpreamplifier input capacitance)
• Sensor capacitance higher than initially
  expected noise performance greatly affected.
  Room for improvement in next chip submission

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Response to infrared laser

• Infrared laser used to emulate charge released by
  particle
• ?1060 nm ? absorption coefficient10 cm-1 in Si
  ? pixel can be back illuminated
• Total charge released equivalent to 6 MIPs
• Charge released in a broad region under the
  sensor fraction of the charge collected by pixel
  depends on the laser spot intensity profile (not
  well known yet)

• Largest charge collected in the largest pixel.
• Charge does not scale linearly ? laser spot
  larger than the pixel area and with non uniform
  profile
• Results roughly compatible with a gaussian laser
  spot profile of about 50 ?m

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Calibration with 55Fe X-ray

• Peak value of the shaper output
• blue - 55Fe source (5.9 keV)
• green - No source (same acquisition time)

• Soft X-ray from 55Fe source used to calibrate
  pixel noise and gain in channels with no
  injection capacitance

?105 mV ?12 mV
Threshold set cuts this region

• 5.9 keV line ? 1640 e/h pairs

• with charge entirely collected clear peak _at_ 105
  mV -gt gain400 mV/fC
• below 100 mV excess w.r.t. noise events lt-
  charge only partially collected
• Using 55Fe gain calibration pixel noise 8 mV
  ENC125 e-
• Signal from simulation ? 1500 e-
  S/N expected 12

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Response to 90Sr electrons
Response to M.I.P from 90Sr beta source used to
measure S/N ratio
15 die in Si
45 are M.I.P Landau peak
40 release more than a M.I.P, they deform Landau
shape or saturate the shaper
Acquisition triggered by coincidence scintillator
pixel signal above threshold (set _at_ 0.5 MIP)
Setup not easy as it seems you need to fire a
single pixel 30x30 ?m2 !
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Response to 90Sr electrons

• Peak value of the shaper output
• blue - 90Sr beta source
• green - No source

• Landau peak clearly visible _at_80 mV
• Using M.I.P signal from 90Sr and average pixel
  noise
• S/N10
• Using gain measured with 55Fe, M.I.P most
  probable energy loss corresponds to about 1250 e-
  
• Fair agreement with sensor simulation ? 1500 e-
  expected for pepi layer thickness ? 15 ?m. Hint
  on the process secrets!

Threshold set cuts this region
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Second chip layout
Pixel Matrix
Single Pixel channels
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