Applied%20Logic%20

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Applied Logic Computation in System Design-
An invitation to ALCom Lab

• Jie-Hong R. Jiang
• ???
• DEE/GIEE
• National Taiwan University

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About ALCom Lab

• Founded in August 2005
• Caring about solving a good problem cleverly
• We are cooking a pleasant research environment
  and a culture of creativity
• Regular boardgame nights
• Puzzle solving
• Focus/study groups
• Aiming high and identifying a niche

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New blood wanted!

• We desperately eager for talented students
  joining us to claim challenging and exciting
  research projects
• Yes, you are one of the talents!

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Where are we heading?
Verification
Optimization
Foundations
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Challenges

• Verification
• 60-80 design time is spent on verification
• 3-to-1 head count ratio between verification
  engineers and logic designers
• Optimization
• Stringent design constraints on
  power/timing/yield, etc.
• Foundations
• Design beyond silicon? New models of computation?

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Equivalence verification
Algorithm
?
Architecture 1 (e.g. synchronous)
Architecture 2 (e.g. asynchronous)
?
?

register-transfer level
?

?

gate level 1
gate level 2
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Property verification

• Identify invariants
• Apply induction

Ex.

1. 2 n

n n-1 1

Ex.
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Synthesis optimization
Existing IP
I
O
X
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More info

• Contact me at
• jhjiang_at_cc.ee.ntu.edu.tw
• Consult webpage at
• http//alcom.ee.ntu.edu.tw
• http//cc.ee.ntu.edu.tw/jhjiang