On the Design of a Photonic NetworkonChip

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On the Design of a Photonic Network-on-Chip
NOCS 2007 Paper 2.1

• Assaf Shacham, Keren Bergman, Luca P. Carloni
• Columbia University

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Outline

• Motivation
• Networks on chip for chip multiprocessors
• The photonics opportunity
• Photonic NoC
• Justification low power
• Design issues topology, flow control, injection
• Performance study path multiplicity, message
  sizing
• Conclusions

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Chip MultiProcessors (CMP)
CELL BE IBM 2005
Montecito Intel 2004
RAW MIT 2002
Polaris Intel 2007
Niagara Sun 2004
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Networks on Chip (NoC)

• Shared, packet-switched, optimized for
  communications
• Resource efficiency
• Design simplicity
• IP reusability
• High performance
• But no true relief in power dissipation

Kolodny, 2005
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Photonics Advantages and Drawbacks

• Advantages
• Bit rate transparency transmission/switching
  power independent of bandwidth
• Low loss power independent of distance ( in
  chip-scale distances)
• Wavelength Division Multiplexing huge
  transmission bandwidth via wavelength-striping
• Seamless optical I/O
• Drawbacks
• No buffers
• No in-flight processing

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Photonic Integration
Infinera, 2005
IBM, 2007
Lipson, Cornell, 2005
Luxtera, 2005
Bowers, UCSB, 2006
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Photonic NoC The Challenges

• 3-D integration of photonic elements (modulators,
  receivers, waveguides, switches) with standard
  CMOS processes.
• Getting light onto the silicon chip
• Simplifying fabrication to lower cost
• Network architecture and design
• Building blocks
• Routing
• Flow control
• Topology

• Hot research topics
• Si photonics
• 3D integration
• optical interconnects

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Photonic NoC The Challenges

• 3-D integration of photonic elements (modulators,
  receivers, waveguides, switches) with standard
  CMOS processes.
• Getting light onto the silicon chip
• Simplifying fabrication to lower cost
• Network architecture and design
• Building blocks
• Routing
• Flow control
• Topology

• Hot research topics
• Si photonics
• 3D integration
• optical interconnects

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Photonic On-Chip Network

• Goal Design a NoC for a chip multiprocessor
  (CMP)
• Electronics
• Integration density ? abundant buffering and
  processing
• Power dissipation grows with data rate
• Photonics
• Low loss, large bandwidth, bit-rate transparency
• Limited processing, no buffers
• Our solution a hybrid approach
• Data transmission in a photonic network
• Control in an electronic network
• Paths reserved before transmission ? No optical
  buffering

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Building Blocks (1) Photonic Switching Element

• Broadband ring-resonator switch
• OFF state
• passive waveguide crossover
• negligible power
• ON state
• carrier injection ? coupling into
• ring ? signal switched
• Initial (narrowband) implementations
• Xu et al., Nature 2005

Xu et al. Opt. Lett., 15(2), 2007
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Building Blocks (2) 4x4 Photonic Switch

• 4 PSEs grouped with electronic control
• 4 waveguide pairs I/O links
• Electronic router
• High speed simple logic
• Links optimized for
• high speed
• Small area (0.005mm2)
• Nearly no power consumption in OFF state

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Topology

• Regular 2-D planar topology
• folded torus smaller diameter, longer links
• Compatible with CMP layout
• Based on 4x4 photonic switches
• Gateway Access Points (GAP)
• Optical packet injection/ejection
• Seamless off-chip connection
• Overprovisioning of photonic paths
• Compensates for lack of buffers
• Facilitated by small switch footprint
• Optimized vs. latency

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Flow control

• Path-setup packet
• destination-address
• flow-id
• priority
• Back-propagating optical pulse
• Large bandwidth optical message
• Path-teardown packet

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Comparative Power Analysis DAC 07

• 6x6 tiled CMP
• Very large bandwidths per core
• Peak 800 Gb/s
• Average 512 Gb/s
• Compared designs
• Electronic on-chip network
• Hybrid photonic on-chip network
• Performance per watt

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Power Analysis Results DAC 07

• Electronic NoC
• Copper lines are bandwidth-limited
• Parallelism used to attain large bandwidth
• Wide busses and large buffers are power hungry
• Multiple hops require regeneration
• NoC power exceeding 100 W (prediction for 22 nm)
• Photonic NoC
• Message generation 2.3 W (assuming 0.11 pJ/bit)
• Photonic switching 0.04 W practically
  negligible
• Network control 0.8 W (and scaling down with
  technology)
• Total 3.2 W

TX
RX
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Network Simulation Model

• OMNeT modular, open-source, event-driven
  simulation environment.
• Define network elements using C
• PSE, 44 switch, Gateway
• Connect them to construct hierarchical full-scale
  network
• Explore the design space
• Topology
• Routing
• Flow control
• Traffic patterns
• And many more

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Path Multiplicity

• Parallel paths (subnets) can be added to reduce
  contentions and latency

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Message Sizing (throughput)
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Message Sizing (latency)
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Conclusions

• Electronic NoCs dont fundamentally reduce power
  consumed on intrachip communications
• Remarkable achievements in silicon photonics
• Photonic NoCs can dramatically reduce power for
  high bandwidth communications on- and off-chip
  (inter-node in large scale systems and external
  memory)
• There are numerous challenges
• Fabrication
• Integration
• Network design
• Photonics enables new systems paradigms!