LCD Controller

1
LCD Controller

• Example Design Review
• Dr. Gruenbacher
• April 12, 2004

2
Topics

• Objectives
• Block Diagram Model
• Interface Definition
• Design Description
• Design and Test Plan
• Current Status
• Issues

3
Design Objectives

• Use the Liquid Crystal Display (LCD) on the
  Altera SOPC board to display information
• Implement a design on the APEX 20KE452-1X that
  interfaces to the Hitachi LCD controller

4
System Block Diagram
5
External Interfaces

• Asynchronous Reset (ar, active low)
• Clock 66 MHz
• Divide by 2(13) for internal clock rate
• Hitachi LCD Controller bus
• RS Register Select (0Instruction, 1Data)
• R/(W) Read/Write bar
• E starts a bus transaction when 1
• DB7-DB0 bidirectional data lines
• DB7 indicates a busy flag during reads
• Intermediate SN74LVT245BDW controlled by the RW
  line

6
Design Description

• Clock divider
• // Generate slower FSM clock by dividing clk_fast
  by 214 always _at_(negedge ar or posedge
  clk_fast)
• if(ar) clkdiv_cntr lt 4'b0
• else clkdiv_cntr lt clkdiv_cntr 1
  
• assign fsm_clk clkdiv_cntr13
• Bus state machine
• Data state machine

7
Bus state machine
begin_write is asserted by the data state
machine busy is the value of bit DB7during a
read wr_done is used to indicate the main state
machine that a write transaction has finished
(used by data state machine)
8
Bus code

• Three state (bidirectional) implementation
• assign lcd_db lcd_rw ? write_data_reg
  8'bzzzzzzzz
• Data is registered (clocked) to prevent
  glitches
• always _at_(negedge ar or posedge fsm_clk)
• if(ar)
• write_data_reg 8'b0
• else
• write_data_reg write_data
• Runs off clock fsm_clk

9
Data state machine
10
Data state machine code (Ex.)

• always _at_(negedge ar or posedge fsm_clk)
• if(ar)
• cs Reset
• else
• cs ns
• always _at_(cs or wr_done)
• begin
• case(cs)
• D // Write the
  letter D
• begin
• write_data lt 8'h44
• write_rs lt 1'b1
• begin_write lt 1'b1
  
• ns lt Wait_D
• end
• Wait_D
• begin

11
Design and Test Plan

• All designs and test benches written in Verilog
• Behavioral compile and simulation using Synopsys
  VCS
• Test bench will allow verification of intended
  bus protocol, but will (cannot) verify Hitachi
  LCD operation
• Synthesis using Synopsys Design Compiler
• final target will be APEX20K400
• Final place and route using Altera QuartusII
• Test and verification on APEX SOPC board
• Visual confirmation of the characters displayed
  on LCD

12
Current Status

• Design
• 100 code written
• 100 synthesized in Design Compiler
• 100 place and route in Quartus
• Test bench
• 100 written
• 100 verified in VCS

13
Issues

• Resolved
• Maximum bus speed to LCD Controller
• Runs well with 8 kHz fsm_clk
• Outstanding
• Busy flag read from LCD Controller
• Reading the busy flag caused a space to be
  inserted between each character
• Removing/bypassing the read cycles has
  temporarily avoided this problem

14
Summary Info.

• Blah, blah, blah..
• Other information you may provide in your
  presentation
• Individual assignments/responsibilities
• Design Hierarchy (how you are breaking the design
  into separate modules)
• ???