332:437 Lecture 7 Verilog Hardware Description Language Basics

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332437 Lecture 7Verilog Hardware Description
Language Basics

• Motivation for Hardware Description Language
• Tool flow
• FPGA Design Methodology and Synthesis
• Logic Synthesis Problems
• Summary

Material from The Verilog Hardware Description
Language, by Thomas and Moorby, Kluwer Academic
Publishers, VHDL for Programmable Logic, by
Kevin Skahill, Addison Wesley Longman.
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Motivation

• Now possible to automatically design hardware
  using a computer program (Synopsys
  design_analyzer)
• Translate high-level hardware description
  language (Verilog or VHDL) automatically into
  logic gates
• Massive saving of time for hardware design
• Widely used at all electronics companies
• Problem Resulting hardware design is not always
  good
• Designer must check the design to determine its
  quality
• If unacceptable, redesign manually using K-maps
  and lower-level hardware synthesis tools
• Example NJ company went out of business because
  they used a bad design created with VHDL
• Too many logic gates, too slow, too expensive

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Synopsys System at Rutgers

• Industrial Cost 50 licenses X 1 million /
  license 50 million
• University Cost 3 X 5000 15000
• Tools used in DSD
• design_analyzer Translates Verilog into logic
  gates
• vcs Verilog behavioral and logic simulator
• Good check to make certain that design_analyzer
  correctly created the logic
• Many other tools are in the tool suite

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Verilog Language

• Concurrent hardware description language
• Expresses parallelism in the hardware
• DO NOT code Verilog like a C or FORTRAN program
• Serializes the hardware operations
• Leads to a BIG increase in the amount of the
  hardware
• design_analyzer adds interlock logic gates to
  make sure that the hardware runs serially --
  unnecessary

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Choice of Hardware Description Language

• VHDL
• Used in all Dept. of Defense (DoD) military
  system designs
• Used throughout Europe, Japan, and IBM
• Has problems with type conversions between
  Boolean and arithmetic
• Verilog
• Preferred in the commercial electronics industry
• Best for converting data types between bit vector
  and arithmetic notations
• Best for configuring large designs produced by
  large design teams
• Best for describing low-level logic (more
  concise)
• Reality Probably need to know both languages
• Impossible to say which is better matter of
  taste

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Shortcomings of Verilog or VHDL

• You lose some control of defining the gate-level
  circuit implementation
• You dont have time to do that, anyway
• Logic synthesized by the Verilog compiler is
  sometimes inefficient
• A real problem Must learn to explain the
  design to the compiler in the right way to get
  maximum hardware parallelism, which leads to the
  best design
• Quality of synthesis varies from tool to tool
• Use Synopsys for high quality used at Intel,
  IBM, Agere, everywhere knowing this helps you
  get a job

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Activities of Design at Levels of Design
ARCHITECTURE BEHAVIORAL REGISTER TRANSFER
Verilog/VHDL LOGIC SWITCH LEVEL CIRCUIT
(TRANSISTORS) LAYOUT TEST PATTERNS FABRICATION
LINE
Synopsys Design Analyzer
Synopsys Behavioral Simulation
Synopsys Logic Sim.
Cadence Verilog-XL
SPICE and Cadence Spectre
Cadence LayoutPlus
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Design Activities

• Implemented by complex Computer-Aided Design
  programs
• You must know how to parameterize these correctly
  to get correct results
• Estimation Estimate likely design parameters
• Synthesis Translate design into lower level of
  representation
• Simulation Mimic design behavior at level of
  representation to see if it is correct
• Analysis Analyze design parameters at a level

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Fitting and Routing

• Fitting Fit logic produced by synthesis, place
  it onto a particular programmable logic device,
  transforming the logic as needed
• Place Route Place logic in a particular
  combinational Logic Block on an FPGA, such that
  the wiring delay between the block and others is
  acceptable
• Must place critical circuit portions together to
  minimize wiring delays
• Propagation delay of signals depends
  significantly on routing delay

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Design Verification

• Can simulate the placed routed device with
  fairly realistic logic gate delays
• Use Synopsys PrimeTime static timing analyzer
• Simulation always essential to verify correct
  design behavior
• Can avoid making application-specific integrated
  circuits (ASICs), burning field-programmable gate
  arrays (FPGAs), or making full-custom chips that
  do not work
• Must simulate at both behavioral and logic levels
• Behavioral simulation finds logic errors
• Logic simulation verifies that Synopsys designed
  logic correctly

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FPGA Modern Design Methodology
always mumble mumble blah blah
gates, gates, gates,
Synthesis
Synthesizable Verilog
Place and Route
LE 1
LE 2
Logic Elements in FPGA Chip
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Whats a Logic Element (LE)?
A mux selects which element of memory to send to
output

• Arbitrary programmable Boolean function of K
  inputs
• K4 in our particular example. Usually see K3,
  4, 5 in real FPGAs
• It has a memory you download to the memory to
  program the device
• You also program connections between these
  Logical Elements
• Synthesis tool partitions logic into groups of
  5-input functions

Really just a 1-bit memory
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What Do We Mean by Synthesis?

• Logic synthesis
• A program that designs logic from abstract
  descriptions of the logic
• takes constraints (e.g. size, speed)
• uses a library (e.g. 3-input gates)
• How?
• You write an abstract Verilog description of
  the logic
• The synthesis tool provides alternative
  implementations

constraints
Verilog blah blah blah
synthesis
or
library
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An Example

• Whats cool?
• You type the left, synthesis gives you the gates
• It used a different library than you did.
  (2-input gates only)
• One description suffices for a variety of
  alternate implementations!
• ... but this assumes you know a gate level
  implementation thats not an abstract Verilog
  description.

module gate (f, a, b, c) output f input a, b,
c and A (a1, a, b, c), B (a2, a, b,
c), C (a3, a, o1) or D (o1, b, c), E (f,
a1, a2, a3) endmodule
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What Do We Want Here?

• Goal
• To specify a combination ckt, inputs-gtoutputs
• in a form of Verilog that synthesis tools will
  correctly read
• and then use to make the right logic
• And...
• We know the function we want, and can specify in
  C-like form...
• but we dont now the exact gates (nor logic
  elements) we want the tool to figure this out.

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Synthesis and Libraries

• Synopsys can synthesize hardware for the
  components in a wide variety of libraries, as
  well as for complex programmable logic devices
  (CPLDs) and field-programmable gate arrays
  (FPGAs)

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Problems with Automatic Logic Synthesis

• Verilog synthesis may frequently interpret code
  differently from Verilog simulation
• Unneeded Logic May Not Be Detected
• Both circuits are equivalent

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Ease of Synthesis Depends on Description Form
Easier to synthesize
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Summary

• Motivation for Hardware Description Language
• FPGA Design Methodology and Synthesis
• Logic Synthesis Problems
• Tool flow