A novel approach to reduce test power consumption

1
A novel approach to reduce test power consumption

• Santanu Chattopadhyay
• Shantanu Gupta
• Tarang Vaish
• Department of Computer Science and Engineering,
• Indian Institute of Technology Guwahati

2
Presentation Outline

• Motivation
• Scan based DFT
• Previous Works
• Proposed approach
• Simulation results
• Conclusions and future work
• References

3
Presentation Outline

• Motivation
• Scan based DFT
• Previous Works
• Proposed approach
• Simulation results
• Conclusions and future work
• References

4
Motivation

• Cost constraints on packaging require a tight
  limitation on power dissipation.
• Power consumed during test is as much as twice
  the normal mode operation 10
• Power consumption is attributed to the high
  switching activity during test.
• Thus reducing test power engenders lower
  production costs.

5
Presentation Outline

• Motivation
• Scan based DFT
• Previous Works
• Proposed approach
• Simulation results
• Conclusions and future work
• References

6
Scan based DFT

• Most common Design for test (DFT) method
• Sequential elements modified to scan cells and
  form a serial shift register
• In scan mode, cell shifts in value from previous
  scan cell
• In normal mode, data loaded in parallel from
  combinational part

7
Test Scan Architecture
PO
PI
SFF
SCANOUT
Combinational logic
SFF
SFF
TC
Not shown CK or MCK/SCK feed all SFFs.
SCANIN
8
The Process

• Scan-in of test vectors in the chain composed of
  D type flip-flops
• Circuit Under Test (CUT) takes the scanned-in
  test vector as input
• Response from the CUT is given out to the chain,
  which is later scanned-out for signature
  comparison

9
Conventional Scan Cell Testing (CSCT)

• Conventional scan architecture (Q-D)

Q
D
Q
Q
Q
D
D
D
SIN
SOUT
\Q
\Q
\Q
\Q
Test vector 1011
trans
0
-
-
-
-
10
Conventional Scan Cell Testing (CSCT)

• Conventional scan architecture (Q-D)

Q
D
Q
Q
Q
D
D
D
SIN
SOUT
\Q
\Q
\Q
\Q
Test vector 1011
trans
0
-
-
-
-
1
0
-
-
-
11
Conventional Scan Cell Testing (CSCT)

• Conventional scan architecture (Q-D)

Q
D
Q
Q
Q
D
D
D
SIN
SOUT
\Q
\Q
\Q
\Q
Test vector 1011
trans
0
-
-
-
-
1
0
-
-
-
1
0
-
-
1
12
Conventional Scan Cell Testing (CSCT)

• Conventional scan architecture (Q-D)

Q
D
Q
Q
Q
D
D
D
SIN
SOUT
\Q
\Q
\Q
\Q
Test vector 1011
trans
0
-
-
-
-
1
0
-
-
-
1
0
-
-
1
0
1
-
1
1
13
Conventional Scan Cell Testing (CSCT)

• Conventional scan architecture (Q-D)

Q
D
Q
Q
Q
D
D
D
SIN
SOUT
\Q
\Q
\Q
\Q
Test vector 1011
trans
0
-
-
-
-
1
0
-
-
-
1
0
-
-
1
0
1
-
1
1
1
2
1
1
0
Total 3
14
Presentation Outline

• Motivation
• Scan based DFT
• Previous Works
• Proposed approach
• Simulation results
• Conclusions and future work
• References

15
Previous Works

• ATPG Stage
• Using don't-care bits to improve the correlation
  between two consecutive test vectors
• Redundancy based approach like fault dropping
  (filters out redundant test vectors which target
  same faults).

16
Previous Works

• Post ATPG Stage
• Scan cell reordering based techniques
• Drawback Long and congested wire routing
• Timing problems and decoder buffer problems
• Reordering of test vectors
• A combination of above two approaches
• Adding extra DFT logic to reduce switching
  activity
• Drawback Area overheads are high

17
Presentation Outline

• Motivation
• Scan based DFT
• Previous Works
• Proposed approach
• Simulation results
• Conclusions and future work
• References

18
Optimized Scan Cell Testing (OSCT) Our Approach

• A three step algorithm

Scan Architecture Modification
Test Vector Adaptation
Test Vector Reordering
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Scan Architecture Modification (SAM)

• Does not involve scan cell reordering.
• We suggest including \Q-D type of connections at
  well chosen position. (instead of only Q-D type
  connections)
• Type of connection is dependent upon the set of
  test vectors and responses provided by ATPG.

D
Q
D
Q
\Q
\Q
20
SAM How do we do it?

• Formula deciding flip-flop connection at
• ith index of the scan chain
• Cost incurred (in terms of number of transitions)
  is compared at every index of the scan chain to
  choose between Q-D and \Q-D

21
SAM A simple example

• We calculate the VBitTotal (VBT) and RBitTotal
  (RBT) for the input and response vectors
• Using these values, we can determine transition
  Cost at every scan chain index

Vector
Response
VBT011-001 VBT111-000 VBT211-003
RBT011-000 RBT111-002
RBT211-003 VBT010-013 VBT110-014
VBT210-011 RBT010-014
RBT110-012 RBT210-011
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SAM A simple example
Cost011-00 15 Cost111-00 12
Cost211-00 4 Cost010-01 1
Cost110-01 4 Cost210-01 12
\Q D \Q D
Q D
Q
D
Q
Q
Q
D
D
D
SIN
SOUT
\Q
\Q
\Q
\Q
Thus depending upon the Cost values we choose
among Q-D and \Q-D type of connections
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Test Vector Adaptation (TVA)

• \Q-D connection flip the bits of test pattern
  passing through them.
• Consequently, the adaptation of the test vectors
  is required to have the original vector after the
  scan-in.
• Rule for adaptation
• Flip a bit if it passes odd number of \Q-D
  connections
• Keep it the same otherwise

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TVA A simple example

• Take 1011, with target architecture

Q
D
Q
Q
Q
D
D
D
SIN
SOUT
\Q
\Q
\Q
\Q
1
0
1
Original vector
1
Even \Q-D
Odd \Q-D
Even \Q-D
Even \Q-D
1
1
1
Adapted vector
1
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Optimized Scan Cell Testing (OSCT)

• Modified Scan design (with \Q-D)

Q
D
Q
Q
Q
D
D
D
SIN
SOUT
\Q
\Q
\Q
\Q
Test vector 1111 (adapted)
trans
0
-
-
-
-
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Optimized Scan Cell Testing (OSCT)

• Modified Scan design (with \Q-D)

Q
D
Q
Q
Q
D
D
D
SIN
SOUT
\Q
\Q
\Q
\Q
Test vector 1111 (adapted)
trans
0
-
-
-
-
1
0
-
-
-
27
Optimized Scan Cell Testing (OSCT)

• Modified Scan design (with \Q-D)

Q
D
Q
Q
Q
D
D
D
SIN
SOUT
\Q
\Q
\Q
\Q
Test vector 1111 (adapted)
trans
0
-
-
-
-
1
0
-
-
-
1
0
-
-
0
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Optimized Scan Cell Testing (OSCT)

• Modified Scan design (with \Q-D)

Q
D
Q
Q
Q
D
D
D
SIN
SOUT
\Q
\Q
\Q
\Q
Test vector 1111 (adapted)
trans
0
-
-
-
-
1
0
-
-
-
1
0
-
-
0
1
0
-
1
0
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Optimized Scan Cell Testing (OSCT)

• Modified Scan design (with \Q-D)

Q
D
Q
Q
Q
D
D
D
SIN
SOUT
\Q
\Q
\Q
\Q
Test vector 1111 (adapted)
trans
0
-
-
-
-
1
0
-
-
-
1
0
-
-
0
1
0
-
1
0
1
0
1
1
0
Total 0
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Test Vector Reordering (TVR)

• Concept of Clash Difference in MSB of last
  test response and LSB of new test vector

0 1 1 1
Response of last test vector
New vector for shift
No Clash
0 1 1 0
Response of last test vector
New vector for shift
Clash
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Test Vector Reordering (TVR)

• Each Clash propagates through the complete FF
  chain.
• (trans) (clashes) X ( FF in scan chain)
• We will reorder test vectors so as to minimize
  the number of clashes, thereby reducing number of
  transitions further.

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TVR How do we do it?

• Classify the test patterns into 4 groups
  represented as 00, 01, 10, 11 of the format
  LSB of Vector, MSB of Response
• List all vectors of group 00
• List one vector from group 01
• List all vectors of group 11
• List all vectors from group 10 and 01
  alternately
• If either of the list exhausts, ignore the
  alternate picking policy and list the remaining
  vectors of the other group.

33
TVR A simple example
(0101, 1001 ) (1100, 1000 ) (0110, 0011
) (1101, 0000 ) (0000, 1001 ) (1101, 0101
) (0100, 0001 )
(0110, 0011 ) (0100, 0001 )
(0110, 0011 ) (0100, 0001 )
All from 00
(1100, 1000 ) (0000, 1001 )
(1100, 1000 )
One from 01
(0101, 1001 )
All from 11
(1101, 0000 ) (1101, 0101 )
(1101, 0000 )
Alternately from 10 and 01
3 Clashes before ordering
(0000, 1001 )
(0101, 1001 )
(1101, 0101 )
0 Clashes after ordering
Division into groups
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Advantages

• Significant test power reduction
• Circumvents scan cell reordering based approaches
  in terms of feasibility
• No interference with circuit parameters like
  delay or area
• No compromise on the fault coverage
• No extra DFT logic

35
Presentation Outline

• Motivation
• Scan based DFT
• Previous Works
• Proposed approach
• Simulation results
• Conclusions and future work
• References

36
Simulation Resultsusing ISCAS89 benchmarks
37
Presentation Outline

• Motivation
• Scan based DFT
• Previous Works
• Proposed approach
• Simulation results
• Conclusions and future work
• References

38
Conclusions and future work

• We were effectively able to reduce number of
  transitions thereby reducing the power consumed.
• 24.4 for s510
• Our method is independent of other parameters
  like delay and fault coverage.
• Future work would involve molding ATPG patterns
  generated to meet our ends.

39
Presentation Outline

• Motivation
• Scan based DFT
• Previous Works
• Proposed approach
• Simulation results
• Conclusions and future work
• References

40
References

• 1 A. Crouch, Design-for-Test for Digital ICs
  and Embedded Core Systems, Number IBSN
  0-13-08427-1 Prentice Hall, 1999.
• 2 V. Dabholkar and S. Charkravarty, Techniques
  for minimizing power in scan and combinational
  circuits during test application, IEEE Trans, on
  Computer Aided Design, 17(12)1325-1333, 1998.
• 3 S. Devadas and S. Malik, A survey of
  optimization techniques targeting low power VLSI
  circuits, In Proc. Of Design Automation
  Conferences, pages 242-247, 2002.
• 4 D.Bryan F.Brglez and K.Kozminski,
  Combinational profiles of sequential Benchmark
  circuits, IEEE ISCAS, 31929-1934, May 1989.
• 5 S. Gerstendorfer and H.J.Wunderlich,
  Minimized power consumption for scan-based Bist,
  In Proc. IEEE International Test Conference Pages
  77-84, 1999.
• 6 H.K.Lee and D.S. Ha, On the generation of
  test patterns for combinational circuits,
  Technical Reports 12-93, Dept. of Elec. Eng.
  Virginia Polytechnic Institute and State
  University.
• 7 I. Bayraktarouglu O. Sinanoglu and A.
  Orailoglu. Scan power reduction through test data
  transition frequency analysis. In Proc. Of
  International Test Conference, pages 844-850,
  2002.
• 8 C. Laundrault P. Girard, L. Guiller and S.
  Pravossoudovitch, A test vector ordering
  technique for switching activity reduction during
  test operation. In IEEE Great Lakes Symposium on
  VLSI, pages 24-27, 1999.
• 9 C. Laundrault Y. Bonhomme, P. Girard and S.
  Pravossoudovitch, Power driven chaining of
  flip-flops in scan architectures. In Proc. IEEE
  International Test Conference, pages 786-803,
  2002.
• 10 Y. Zorian. A distributed BIST control scheme
  for complex VLSI devices. In Proc.11th IEEE VLSI
  Test Symposium, pages 49, 1993.

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Thank You