Title: CS 426 Operating Systems
1CS 426 - Operating Systems
- Class 12
- February 15, 2000
2Thought for the Day
- Human beings,
- who are almost unique in having the ability to
learn from the experience of others, - are also remarkable for their apparent
disinclination to do so. - -- Douglas Adams,
- Last Chance to See
3Todays Cartoon
The cartoon that was here came from Randy
Glassbergens Cartoon of the Day site.
4Todays Agenda
- Paper 1 Assignment
- Hand back Project 1
- Finish Chapter 8 Memory Management
5Reading Assignment
- Chapter 9 Virtual Memory for Thursday (Dr. V.)
6Paper 1 Assignment
- Compile run fork.C on Bama.
- Investigate all the included files and all the
system calls. - Write a short paper explaining
- What the program does
- How it does it (calls, etc.)
- Explain the output.
- Detailed instructions handout, web page.
- Due Feb 24th.
- Any questions on this project?
7Warnings about Papers
- Note well English grammar, spelling,
- This will be graded strictly.
- Get help if you need it!
- At the least, use a spelling checker and a
grammar checker! - Be very careful about plagiarism!
8Project 1
- Average 37/40
- Notes
- Questions 1, 2 3 only marked off if obviously
wrong. - Q 4a What do these plots represent?
- What is the idle process? The PVIEW process?
- Q 6a What applications are running?
- Q 6d Any plot in Performance Monitor like Memory
Usage in Task Manager?
9Chapter 8 Memory Management
- Background
- Logical versus Physical Address Space
- Swapping
- Contiguous Allocation
- Paging
- Segmentation
- Segmentation with Paging
10Memory Protection
- Memory protection implemented by associating
protection bit with each frame. - Valid-invalid bit attached to each entry in the
page table - valid indicates that the associated page is in
the process logical address space, and is thus a
legal page. - invalid indicates that the page is not in the
process logical address space.
11Two-Level Page-Table Scheme
12Two-Level Paging Example
- A logical address (on 32-bit machine with 4K page
size) is divided into - a page number consisting of 20 bits.
- a page offset consisting of 12 bits.
- Since the page table is paged, the page number is
further divided into - a 10-bit page number.
- a 10-bit page offset.
- Thus, a logical address is as follows
where pi is an index into the outer page table,
and p2 is the displacement within the page of the
outer page table.
13Address-Translation Scheme
- Address-translation scheme for a two-level 32-bit
paging architecture
14Multilevel Paging and Performance
- Since each level is stored as a separate table in
memory, covering a logical address to a physical
one may take four memory accesses. - Even though time needed for one memory access is
quintupled, caching permits performance to remain
reasonable. - Cache hit rate of 98 percent yields
- effective access time 0.98 x 120 0.02 x
520 - 128 nanoseconds.which is only a 28
percent slowdown in memory access time.
15Inverted Page Table
- One entry for each real page of memory.
- Entry consists of the virtual address of the page
stored in that real memory location, with
information about the process that owns that
page. - Decreases memory needed to store each page table,
but increases time needed to search the table
when a page reference occurs. - Use hash table to limit the search to one or at
most a few page-table entries.
16Inverted Page Table Architecture
17Shared Pages
- Shared code
- One copy of read-only (reentrant) code shared
among processes (i.e., text editors, compilers,
window systems). - Shared code must appear in same location in the
logical address space of all processes. - Private code and data
- Each process keeps a separate copy of the code
and data. - The pages for the private code and data can
appear anywhere in the logical address space.
18Shared Pages Example
19Segmentation
- Memory-management scheme that supports user view
of memory. - A program is a collection of segments. A segment
is a logical unit such as - main program,
- procedure,
- function,
- local variables, global variables,
- common block,
- stack,
- symbol table, arrays
20Logical View of Segmentation
1
2
3
4
user space
physical memory space
21Segmentation Architecture
- Logical address consists of a two tuple
- ltsegment-number, offsetgt
- Segment table maps two-dimensional physical
addresses each table entry has - base contains the starting physical address
where the segments reside in memory. - limit specifies the length of the segment.
- Segment-table base register (STBR) points to the
segment tables location in memory. - Segment-table length register (STLR) indicates
number of segments used by a program - segment number s is legal if s lt
STLR.
22Segmentation Architecture (2)
- Relocation.
- dynamic
- by segment table
- Sharing.
- shared segments
- same segment number in each process (hard!)
- Allocation.
- first fit/best fit
- external fragmentation
23Segmentation Architecture (3)
- Protection. With each entry in segment table
associate - validation bit 0 ? illegal segment
- read/write/execute privileges
- Protection bits associated with segments code
sharing occurs at segment level. - Since segments vary in length, memory allocation
is a dynamic storage-allocation problem. - A segmentation example is shown in the following
diagram
24Sharing of segments
25Segmentation with Paging MULTICS
- The MULTICS system solved problems of external
fragmentation and lengthy search times by paging
the segments. - Solution differs from pure segmentation in that
the segment-table entry contains not the base
address of the segment, but rather the base
address of a page table for this segment.
26MULTICS Address Translation Scheme
27Segmentation with Paging Intel 386
- As shown in the following diagram, the Intel 386
uses segmentation with paging for memory
management with a two-level paging scheme.
28Intel 30386 address translation
29Comparing Memory-Management Strategies
- Hardware support
- Performance
- Fragmentation
- Relocation
- Swapping
- Sharing
- Protection