Silicon on insulator SOItechniques

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Silicon on insulator (SOI)-techniques

• FYS4310
• Lars Løvlie
• 07.06.06

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Introduction to SOI

• Goal
• To separate a thin device layer from the bulk of
  the wafer
• by inserting an electrically insulating layer.

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• Motivation
• SOI decreases the charge to be moved for
  transistor switching
• Smaller region to deplete for carriers
• Faster switching
• Complete isolation between devicesand substrate
• Fabrication in isolated regions of single crystal
  Si, no need for wells
• Removes parasitic MOS to substrate and no
  latchup

Source SiGen, www.sigen.com
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Advantages and disadvantages
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• Two main strategies of SOI
• gt Implantation
• SIMOX and SIMNI
• Bonding and etchback, BE-SOI
• Direct, high temperature or plasma treatment
• Anodic, moderate temperature and high voltage
• First implantation and bonding, then cleaving
• Smart CutTM (Soitec)
• NanocleaveTM (SiGen)

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SIMOX

• Implantation of an extreme dose of O-ions
  creating amorphous layer around Rp
• Dose 1018 cm-2
• Rp usually 1 um
• Temp. 4-600 oC to partially heal surface
  (maintain crystal)
• High temp. anneal to grow SiO2 grains into a
  continuous SiO2 layer... and to avoid
  OSFTemp. 13-1400 oC
• Dislocation concentration around 103 cm-2, high
  cost

BOX Buried OXide
Source Ibis, www.ibis.com
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SIMNI

• Implant N-ions instead of O-ions
• Need smaller dose, since stochiometric Si3N4
  (43) requires less implant species per Si than
  SiO2 (21)

For all techniques it is common to implant in the
direction where you have maximum channeling to
reduce surface damage due to electronic stopping.
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• Two main strategies of SOI
• Implantation
• SIMOX and SIMNI
• gt Bond and etchback, BE-SOI
• Direct, high temperature or plasma treatment
• Anodic, moderate temperature and high voltage
• First implantation and bonding, then cleaving
• Smart CutTM (Soitec)
• NanocleaveTM (SiGen)

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• Direct bonding

• Fusion bonding
• Grow thermal oxide on one wafer.
• Wet surfaces in DI water
• Prebonding Apply pressure at RT.Hydrogen (OH)
  and Van der Waals bonds
• Bonding Anneal at 1000 oC

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Direct bonding

• ...OR, Plasma Activated Bonding (PAB)
• Grow thermal oxide on one wafer.
• React surface with O-plasma
• Prebonding Apply pressure at RT.
• Bonding Anneal at only 400 oCAvoids problems
  when bonding materials with differing thermal
  expansion coeff.

Sources Senturia, Microsystem Design and
Campbell, The Science and Engineering of ...
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Contact strengths
Source SiGen (paper presented at 2001 MRS
Spring Meeting, www.sigen.com
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Anodic/Field assisted bonding

• Grow thermal oxide on surface of one wafer.
• Bonding Anneal at only 400 oC but with voltage
  1000 V.
• Anions in oxide (or glass) flows to cathode
  setting up E-field and attractive electrostatic
  forces.Low T avoids problems when bonding
  materials with different thermal expansion
  coefficients.

Silicon with no oxide
-
E and current of anions

Silicon with surface oxide
-
Heater
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• Two main strategies of SOI
• Implantation
• SIMOX and SIMNI
• Bonding and Etchback, BE-SOI
• Direct, high temperature or plasma treatment
• Anodic, moderate temperature and high voltage
• gt First implantation and bonding, then cleaving
• Smart CutTM (Soitec)
• NanocleaveTM (SiGen)

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Implant, bond and cleave-methods

• Grow thermal oxide on surface of a wafer, this
  will be the HANDLE (bottom) wafer
• On the DONOR wafer, either (Smart CutTM)Implant
  a dose of 5E16 cm-2 H creating voids and strain
  after anneal.
• OR (NanocleaveTM)Grow (by epitaxy) strained,
  single crystalline Si ontop of a SiGe
  layer.Implant a smaller dose of H in the
  Ge-rich region.
• Use an intense water or gas jet to cleave in the
  region with voids.
• Surface treatment by CMP, etch or CVD

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State-of-the-art

• sSOI strained SOI
• Strained Si ontop of SiGe
• Higher mobility gives larger drive current in
  MOS-channels
• Already being used
• SOD Si-On-Diamond
• Diamond has larger heat conduction
• Better heat dissipation through substrate will be
  increasingly important
• SOD might never by used for IC-production, but
  very cool

Sources physicsorg.com and Memc Inc.,
www.memc.com
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Sources www.compoundsemiconductor.net and Sarah
Olsen et. al, IEEE Transactions on Electron
Devices, Vol. 50, No. 9
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Sources

• Web
• www.sigen.com
• www.soitec.com
• www.compoundsemiconductor.net
• www.ibis.com
• (The almighty) www.wikipedia.org
• Litterature
• S. Campbell, The Science and Engineering of
  Microelectronic Fabrication
• S. Senturia, Microsystem Design
• B. Streetman, Solid State Electronic Devices
• Maaike M. V. Taklo, Wafer bonding for MEMS
• Articles
• Various (Mainly through ISI Web and Elsevier)

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• Motivation for MEMS

• Bonding makes possible structures in real 3D by
  bonding patterned/etched wafers together
• Si to Si
• Glass to Si
• Si (device layer) SiO2 Si (Bulk)

Source Taklo, Maaike M. Visser (edited)