The Biggascale Emulation Engine

1
The Biggascale Emulation Engine

• Chen Chang
• Kimmo Kuusilinna
• Berkeley Wireless Research Center
• January 2, 2002

2
Whats BEE?

• A real time hardware emulator built with multiple
  high density Field Programmable Gate Arrays
  (FPGAs)
• Designed to directly emulate the digital portion
  of the chip and interface with the analog
  front-end.
• Fully automated design flow from Simulink to FPGA
  configuration bit stream.

3
BEE Architecture

• Wing Muscle Processing Board
• Total 20 Xilinx VirtexE 2000 chips, 16 for
  processing, 4 for interchip routing
• 16 ZBT SRAM chips, 1MB each.
• Nerves Control module
• Intel StrongARM 1110, on board 10 Base-T
  Ethernet, Linux OS
• Compound Eyes Radio Rx/Tx Board
• 2.4 GHz transceiver, Ultrawide-band transceiver
• Brain Design Flow
• From Simulink MDL to FPGA bit stream

4
BEE Hive
Analog Front-end
Network
LVDS
Dedicated Ethernet
Integrated Design Flow
FPGA Bit Stream Conf File
Simulink MDL
ASIC Layout
5
BEE Processing Board
48 bit buses
6
Processing Board PCB
Boar Size 53 X 58 cm No. of Layer
22 Technology 4 Mil Trace Total Components 3400
Bypass Capacitors 2409
7
Off Module Riser I/O Cards
68 Pin HD SCSI Connectors 48 signals per
connector
Source (Xilinx only)
LVDS Termination Resistor Arrays
Destination
400 pin VHDM-HSD Right Angle PCB Connector
8
Riser I/O Card PCB
9
Controller Module

• 206MHz StrongARM 1110 Processor
• 32MB SDRAM
• 16MB Flash ROM
• 10Base-T Ethernet with RJ45 jack
• Compact Flash slot for expandability
• Linux Kernel 2.4 as OS
• Remote FPGA configuration and read-back through
  GPIO

10
Power Distribution System
11
Power Board
12
Power Board PCB
13
Processing Board Power Planes
Core 1.8V
Q0
Q1
SRAM 3.3V
Internal 2.5/3.3V
Q2
Q3
External 2.5/3.3V
Analog 3.3V
14
BEE Design flow Goals

• Auto-generation of FPGA bit stream and inter-chip
  place-and-routing configuration from system level
  design (i.e., Simulink MDL).
• Full integration with SSHAFT flow
• Computational component level equivalency between
  ASIC BEE implementation

15
Commercial Xilinx Design Flow
Simulink MDL
System Generator
VHDL Lib
Core Gen Lib
Top Level VHDL
Core Parameter
Component VHDL
Xilinx ISE
Bit stream
16
Xilinx Design Flow Limitations

• Designs are limited to Single FPGA chip
• Parallel computation blocks are not efficiently
  utilized (i.e., FFT)
• High level DSP blocks do not correspond to the
  same architecture from ASIC design

17
BEE Design flow
Simulink MDL
System Generator
Xilinx Core Lib
Chip Level VHDL
Xilinx ISE
FPGA Bit Files
18
Key parts in BEE design flow

• Board-level System Generator (BSG)
• Component block library
• BEE configurator

19
Existing BSG Flow
20
Future BSG Flow
21
Component block library

• parameterized system level blocks
• Bit-width
• Pipeline stages (latency)
• Output bits truncation
• Customerizable block set library
• Different Architecture

22
Basic Block Sets
23
DSP/COM Block Set
24
Interface Control Blocks
25
Custom-built Library

• Same architecture as ASIC design
• Alternative Control generation with SF2VHDL

VHDL
Subsystem
Black Box
Native Simulink Blocks
I/O Ports
26
BEE Configurator
Bit-stream Files
BEE Processing Unit
BEE Configurator
Ethernet
Partition Configuration File
27
Current Status

• Hardware
• PCB design Complete
• Assembled system in March 2002
• Software
• Working Design Flow with Xilinx System Generator,
  using manual board-level partition
• Automatic board-level routing under development