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Poster1

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The Promela model is translated with the aid of Bison and Flex to a language compatible with the Synthesis tools for FPGAs (HandelC). __ Main Input Main Output – PowerPoint PPT presentation

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Title: Poster1


1
Reliable SW/HW Co-Design for Wireless
Communication System Integrating the Spin Model
Checker and Celoxica's DK Suite
Stefanos Skoulaxinos Dept of Engineering and
Computer Science, Heriot-Watt University,
Edinburgh, UK
Special Thanks to
Development of Wireless Communication System -
LRID Tag
Run Time Monitoring and Exception Handling
(developed in DK Suite)
Development Lifecycle
System Operation
Monitoring Scheme Watch Dog Timers
Multi-Layered Monitoring
Tag Location Process
Formal Verification of Tag Protocol
System View - Base Station
System View - Remote Station
Operation
Remote Station Controller CoolRunner
Formal Verification is performed in the Spin
Model Checker. Spin is considered one of the
most efficient software model checkers currently
used in Safety critical mission including NASAs
mission to Cassini (Saturn) and Mars Pathfinder.
Front End API
C Compiler
UART
Antenna / RF
Process Execution Overhead
PIC 16F876
PIC 16F876
C Compiler
Base Station Functions Vs Time
Time modulation
1 User Selects Tag to be located at front end
API 2 API updates mode of operation of the FPGA
via PIC micro-controller 3 Base Station FPGA
initiates RF transmission to remote stations 4
Base initiates counting - time of arrival of the
ID 5 Selected Remote Station responds by
transmitting its unique identification sequence 6
ID is received at the base. Time of arrival to
each of 3 antennas is utilised to compute x,y and
z co-ordinates
Base Station Controller Spartan IIE/ Spartan3
C Compiler
msecs
Remote Station Functions Vs Time
Antennas / RF
Conclusions
Reliability Estimation
System Testing
Reliability Estimated using CASRE (developed by
JPL/NASA)
Fault Tolerance Disabled
MTBF18 seconds
Fault Tolerance Enabled
MTBF50 seconds
The research project is a collaboration of School
of MACS (Dependable Systems Group) and EPS in
Heriot-Watt University, Edinburgh, UK. We would
also like to thank the Institute for System Level
Integration (ISLI) and Scottish Embedded Software
Centre in Livingston. For any information please
contact S.Skoulaxinos_at_hw.ac.uk
MAPLD 2005/116
Skoulaxinos
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