Nanometer Scale CMOS Threshold Logic

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United Arab Emirates University College of
Engineering Project Code EEF2-4

• Nanometer Scale CMOS Threshold Logic
• Gates

Supervised by Dr. Mawahib
Sulieman Presented by
Ameena Al-Sumaiti 200105247 Durrea Abbad
Durra 200104834 Rauda Al-Amri 200217846 Suaad
Al-Ateeshi 200202766
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Outline

• History and definition of threshold logic
• Threshold logic gate design implementation
  options
• Gate design method characterization
• Full adder circuit
• Carry look-ahead adder circuit
• Results
• Project impacts

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IEEE Journal of solid state circuits-1996
Threshold logic emerged in the early 1960s as
unified theory of logic gates
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Threshold Logic Gate

• Threshold logic gate represents a digital
  summation.
• Operation of Threshlod Logic Gate
• - Inputs binary variables
• - Outputs binary variables
• Threshold logic gate operation is described by

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Threshold Logic Gate Design Options

• Capacitor Threshold Logic Gate
• B) Conductance Threshold Logic Gate

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A) Capacitor Threshold Logic Gate
Vref Reference voltage, FR Reset phase, FE
Evaluation phase
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B) Conductance Threshold Logic Gate

• Output-wired inverters
• Lerch 1973
• Same weight
• Different weights

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Decision

• The output wired inverters was chosen.
• The reason
• Its simple design and fast performance.
• Floating gate in Neuron MOS transistor (latest
  version of capacitive implementation), which is
  difficult to deal with in designing.

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Gate Design Method

• Select the widths of the inverters transistors
  based on the channel length from the predictive
  technology models.
• Write the threshold function from the Boolean
  function by finding the threshold value.
• Study possible cases of different inputs and
  focus on the critical ones above and below the
  threshold.

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Gate Design Method

• Calculate the resistances (RPMOS RNOMS) and the
  corresponding output voltage.
• Select the appropriate value of KR and calculate
  the width of the buffer transistor

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Example OR Gate Design

1. Parameters From The Predictive Technology Models

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2. OR Gate Threshold Function
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2. OR Gate Threshold Function
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3. Possible Cases for OR Resistor Level
Implementation

• Case 1 a and b 0 Case 2 a and b
  1 Case 3 a ? b

VGB
VGB
VGB
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4. R triode Calculation
5. Selecting KR

• Where,
• µ Mobility of the carriers
• Cox Capacitance of gate oxide
• W Width of the transistor
• L Length of the transistor
• VGS Gate Source Voltage
• Vth Threshold voltage

To achieve the right value of KR, VGB1 should be
gt VIH and VGB2 lt VIL .
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• NMOS parameters calculated for L 90nm, 65nm
  and 45nm
• PMOS parameters calculated for L 90nm, 65nm
  and 45nm

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• VIH and VIL calculated for L 90nm, 65nm and
  45nm

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OR Gate Design

• Parameters considered for L 90nm, 65nm and
  45nm

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Characteristics of the OR Gate of L 90nm, 65nm
and 45nm

• OR gate power dissipation
• Using WinSpice program
• There is no power dissipation problem when moving
  to smaller technologies, because no leakage
  current is significantly affecting.

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2. OR Gate Propagation Delay

• The propagation delay is defined as the time
  difference between 50 of the input to 50 of the
  output.
• As the technology gets smaller the delay
  increases.

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Threshold Logic Gates Designs

• Following the same procedure of designing OR gate
  the following designs were achieved

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Full Adder

• The adder is composed of two main parts that are
  the sum and the carry.
• Full adder can be implemented using both the
  majority gate and the 1 1 1 2 gate.
• The majority gate is used to determine the output
  carry while the sum is implanted as 1 1 1 2
  gate.

S a b Ci 2Co - 2.5 Co a b Ci - 1.5
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Carry Look-ahead Adder

• It is made of 4 classes of blocks
• Generate AND operation
• Propagate OR operation
• 1 1 2 GK PK . GK-1
• 1 1 1 2 S (a . Co)(b . Co)(Ci . Co)(a .
  b . Ci)

FASTER
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Results
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Project Impacts

• This project is a new trend since it deals with
  nano-meter scales.
• The project was not associated with any
  environmental issues as the gates were not
  implemented in the laboratory.
• No safety considerations were considered while
  working on this project as its main domain was in
  the field of computer modeling and analysis.
• The cost of the project was 368 as it costs to
  buy Win Spice simulation tool 92/member. No
  other costs were associated with the project.
  

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Conclusion

• Many theoretical results show that threshold
  logic circuits are more powerful and efficient
  than classical Boolean circuits.
• This project is basic point where other complex
  projects can be implemented using the library of
  gates designed, simulated and characterized.
• Our library contains majority gate, 1 1 2 gate,
  AND gate, OR gate, 1 1 1 2 gate, full adder and
  carry look-ahead adder.

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Conclusion

• All the components of the WinSpice library were
  designed and characterized at the nanometer scale
  in terms of delay and power dissipation.
• The nano-meter scale threshold logic gates
  project can be further expanded by implementing
  more complex circuits.

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