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A Single Semester

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A Single Semester Software Defined Radio Transceiver Implementation In a Xilinx Spartant-3 FPGA Steven Brown Justin Ford Kyusun Choi Penn State University – PowerPoint PPT presentation

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Title: A Single Semester


1
A Single Semester Software Defined
Radio Transceiver Implementation In a Xilinx
Spartant-3 FPGA
Steven Brown Justin Ford Kyusun Choi
Penn State University
2
SDR Technology Commercial
AM and FM radio TV Walkie Talkie Cell
phone Cordless phone Garage door opener Car door
opener WiFi/802.11 GPS Shortwave radio Remote
control car/toy

Image source http//www.target.com
3
SDR Technology Military

Image source http//www.deutschdao.com/
http//www.nu-cast.com/ http//www2.hawaii.edu/m
cgraw/Page-Military/Military-Navy/carrier-1.jpg
http//www.mathworks.com http//www.shopingathome
.com/Military20Wireless.htm
4
Hardware Architecture

5
SOFTWARE DEFINED RADIO IN AN FPGA OPERATING AT
CARRIER FREQUENCY

6
Filter Design
Considered Algorithms /
Selected Algorithm

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8
Applications Ultrasound Microscope
  • Ultrasound Microscope
  • Ultrasound Endoscope
  • Ultrasound Pill-camera
  • Ultrasound pill-camera complements
  • the photo pill-camera by providing
  • the following advantages
  • Imaging below the tissues
  • Imaging even in murky liquids
  • Imaging without illumination


Remote medical practice Soldiers
Military Astronauts - NASA
9
Applications Ultrasound Microscope
More ideas Ultrasound communication instead of
RF communication for the image transmission Use
lower frequency ultrasound actuation for
positioning control and propulsion Add
lab-on-a-chip for fluid chemical analysis Add
drug dispenser, temperature sensor, other micro
equipments (micro piezo actuators) in the pill

10
A Novel Scanning Acoustic Microscopy
11
A Novel Scanning Acoustic Microscopy
12
Block Diagram of the first prototype CMOS Chip
13
Functional Diagram of the CMOS Chip
time
14
Simplified Block Diagram of the Chip (1 channel)
15
Pin Configuration
Transducer 9ea Control 2ea Address
5ea Date Out 16ea Power 16ea Clock
2ea VGA Monitor 9ea ETC 5ea
Total 64ea
16
Layout of the full-custom designed CMOS Chip
17
Specifications of the CMOS Chip
  • On-chip Memory
  • SRAM
  • Capacity 3k byte/Channel
  • Speed up to 125 MHz
  • Number of Bits 16 bit
  • Operating Functions
  • Single Channel Mode
  • Multiple Channel Mode
  • Power Supply
  • 3.3V
  • Fabrication Information
  • Chip Size 26.83mm2
  • Package LQFP 64pin
  • Design Rule TSMC 0.35um
  • (2 poly 4 metal)
  • Beam-former
  • Frequency 100 MHz
  • (5 more options b/w 3.9MHz to 125MHz)
  • Pulse Type Sine/Square wave
  • Amplitude of Pulse 3.3V
  • Number of Channels
  • 9 Channels
  • Preamp
  • Gain 1.8 8.6 (Adjustable)
  • Bandwidth 600 MHz_at_5dB
  • 52 MHz_at_19dB
  • VGA
  • Gain -5dB to 15dB
  • Bandwidth 300 MHz
  • A/D Converter
  • Type Pipelined Algorithmic ADC
  • Resolution 8 bit
  • Sampling Rate 250 MS/s

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