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VAST 20002 Computers and Society

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Title: VAST 20002 Computers and Society


1
VAST 200-02 Computers and Society
  • Lecture 4 - Building Hardware and Software
  • Spring 2004

Pentium 4 Chip Die Image couresy Intel Corporati
on
Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
2
Roadmap for the Term Major Topics
  • Course Introduction
  • Computer Systems Overview
  • Computer History
  • Technology Trends
  • The Art of Building Hardware and Software \
  • Current Issues
  • Looking to the Future

3
Readings - HW and SW Design
  • 1. M. Reilly, "Designing an Alpha
    Microprocessor", IEEE Computer, July 1999.
  • 2. C. Hoare, "The Emperor's Old Clothes (Turing
    Award Lecture)", Communications of the
    ACM,    February 1981.
  • 3. D. Parnas, "Software Aspects of Strategic
    Defense Systems", Communications of the ACM,
    December 1985.
  • 4. M. Baer, The New X-Men, Wired, Issue 11.09,
    September 2003(available at http//www.wired.com/
    wired/archive/11.09/xmen.html)

4
Comparing HW and SW Design
  • Hardware
  • Function relatively well-defined (e.g.
    instruction set)
  • Complexity limited by specified function
  • Tight performance constraints
  • Tight resource constraints
  • Manufacturing expense dominates cost in high
    volume
  • Software
  • Function often not well-defined (e.g. list of
    desired features)
  • Complexity is arbitrary (features easily added!)
  • Tight performance constraints (sometimes)
  • Development expense dominates cost

5
Hardware Design
  • Product Definition
  • Exploring Architectural Design Space
  • Technology Development
  • Feasibility Studies
  • CAD Tool Development
  • Register-Transfer-Level (RTL) Design
  • Functional Verification
  • Schematic Design
  • Logic Verification
  • Layout
  • Circuit Verification
  • Fabrication

6
Hardware Design - Product Definition
  • Goal determine performance goals and features
  • What will it do? (i.e., execute IA-32
    instructions)
  • What is its intended application?
  • What is desired performance?
  • How much power will it use?
  • What technology will be used to realize it?

7
Hardware Design - Exploring the Architectural
Design Space
  • What are the major features of the design
  • Major components
  • Size speed
  • Floor plan
  • What is the predicted performance
  • Predict using performance simulation
  • Explore ideas and tradeoffs

8
Hardware Design - Feasibility Studies
  • What kind of low-level components will be used?
    (e.g., flip-flop storage elements)
  • What new circuit designs are possible in new
    technology?
  • What parts of design will be difficult to
    implement?

9
Hardware Design - CAD Tool Development
  • CAD tools are essential for chip design
  • Lower-end design purchase commercial CAD tools
  • Higher-end design combine commercial and custom
    CAD tools

10
Hardware Design - RTL Modeling / Functional
Verification
  • RTL (Register Transfer Level) Modeling
  • Simulation model using Hardware Description
    Language (HDL)
  • Detailed operation of hardware components
  • Detailed interaction between hardware components
  • Becomes the spec. for lower levels of design
  • Functional verification
  • Make sure that RTL design really implements
    spec.
  • Identify and remove design errors (7,855 found
    in Pentium 4 Design)
  • Typical approach
  • Massive simulation using farms of workstations
    or PCs
  • Compare simulation result to reference model

11
Hardware Design - Schematic Design / Logic
Verification
  • Schematic Design
  • Create detailed circuit designs for each RTL
    block
  • Alternative approaches
  • Human designer - higher quality, but longer
    design time
  • Synthesis CAD tool - lower quality, but shorter
    design time
  • Logic Verification
  • Verify that each logic block correctly implements
    RTL
  • Typical approach compare RTL and logic
    simulations

12
Hardware Design - Layout / Circuit Verification
  • Layout Design
  • Convert circuit schematics to geometric mask
    patterns
  • Alternative approaches
  • Human designer - higher quality, but longer
    design time
  • Place/Route CAD tool - lower quality, but shorter
    design time
  • Circuit Verification
  • Verify that layouts correctly realize circuit
    designs
  • Account for non-ideal circuit behavior, e.g.
  • leaky transistors
  • Noise
  • Parasitic components capacitance and resistance
  • Process variation

13
Hardware Design - Fabrication / Debug
  • Tape out Mask patterns sent to fab
  • Manufacture masks
  • Manufacture first chips
  • Turnaround time 4-6 weeks
  • Non-recurring engineering cost (NRE)
    costtooling cost for masks first chips (now
    1 million)
  • Debug
  • Initial testing
  • Measure performance parameters (e.g. clock speed)

14
Hardware Design - Perspective
  • Design process takes years for microprocessors
  • Example Pentium 4
  • RTL Design Began - 1996
  • RTL Design Complete - 1998
  • A-step tapeout - December 1999
  • First packaged parts - January 2000
  • Production - October 2000
  • Verification is crucial, but absence of bugs
    cannot be guaranteed.
  • When bugs are found, workarounds are used until a
    corrected chip goes into production.

Source B. Bentley, Validating the Intel
Pentium 4 Microprocessor, Proceedings Design
Automation Conference, June 2001
15
Case study The Pentium FDIV Bug,1994
  • July 1994 Intel discovers bug in floating point
    divide (FDIV) which resulted in slightly
    inaccurate results. Fix planned for later
    version of chip, but bug not publicized.
  • Sept. 1994 Math professor T. Nicely discovers
    bug and attempts to report it to Intel. When
    they dont respond, Nicely posts bug on the
    Internet.
  • Nov. 7 1994 Electronic Engineering Times breaks
    story in media
  • Nov. 22,1994 Intel responds by attempting to
    minimize the error by calling it a glitch that
    introduces errors in the ninth digit of
    calculations
  • Dec. 12, 1994 IBM Research disputes Intels
    assertion, claims that common spreadsheets would
    have errors approx. once very 24 days. IBM stops
    all shipments of Pentium PCs.
  • Dec. 21, 1994 Intel apologizes, offers to replace
    every faulty Pentium chip at estimated cost of
    300 million

Source D. Patterson and J. Hennessy, Computer
Organization and Design, Morgan-Kaufmann 1997.
16
Coming Up
  • Software Design
  • Is Software harder than hardware?
  • Estimating Software Complexity
  • Software design methods
  • Software Engineering as an emerging field
  • Faults Failures

17
Measuring SW Complexity
  • Source Lines of Code (SLOC)
  • Measures how many lines (statements) in a
    program
  • Useful as a measure of software complexity
  • SOME SLOC Estimates

Sources D. Wheeler, More Than A Gigabuck
Estimating GNU/Linuxs Size, http//www.dewheeler
.com/sloc/ Wikipedia ( wikipedia.org).
18
SW Development - Waterfall Model
Integration
Product Verif.
Product design
System feasibility
Verification
System Test
Detailed Design
Operations Maint.
Verification
Revalidation
Source A Spiral Model of Software Development
and Enhancement, IEEE Computer, May 1988.
19
SW Development - Spiral Model
Source A Spiral Model of Software Development
and Enhancement, IEEE Computer, May 1988.
20
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21
Outline - Course Overview
  • Administrative Details \
  • Course Overview and Introduction
  • Computer Systems Overview
  • General Concepts
  • History and Trends
  • The Creative Process
  • Hardware Design
  • Software Design
  • Current Issues Computers and Society
  • Faults and Failures
  • Privacy and Encryption

22
The Illusion of Privacy
  • 1993 - On the Internet, nobody knows youre a
    dog -- New Yorker cartoon, 1993
  • 1998 On the Internet, nobody knows youre a
    police officer posing as a 14-year old
  • 2002 On the Internet, nobody knows youre a
    Carnivore
  • 2003 On the Internet, nobody knows youre the
    RIAA

23
The Internet - A Network of Networks
  • Common addressing scheme
  • Routers connect networks,
  • TCP/IP
  • IP Addresses - what identifies computers on the
    internet
  • Static addresses - permanently assigned
  • Dynamic addresses
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