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Scooby Doo Gang

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Scooby Doo Gang. 6. Measurement Strategy. Test different board configurations for correctness ... Scooby Doo Gang. 11. Implementation Strategy. Moved SW cycle ... – PowerPoint PPT presentation

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Title: Scooby Doo Gang


1
Scooby Doo Gang
18-545 Final Presentation
2
Those Meddling Kids
  • Anne Pettengill
  • Matt Silverstein
  • Jim Hollifield
  • Jeff Barbieri
  • Jon Hsieh

3
Guest Starring
I love Scooby Snacks!
Adrian Drury - As Our Mom!
4
Design Goals
  • Speed
  • Move Functions to HW
  • attack
  • eval
  • gen
  • Hardware HCI
  • Originally an Array of Alpha-numeric LEDs
  • Dot Matrix LCD Display
  • Download/Upload Play Configurations

5
Changes in Design Goals
  • Different Human Interface
  • LEDs to LCD
  • Added 2nd HC11 to control LCD
  • Added dedicated memory chip for HCI
  • Scheduling Changes
  • Due to HCI Change and Memory Problems
  • Possible Changes
  • Memory Design
  • Some Hardware Functionality

6
Measurement Strategy
  • Test different board configurations for
    correctness
  • LCD displays recognizable pieces and has
    reasonable refresh rate
  • Have Machine play itself for 20 turns
  • Time moves
  • Overall speed up compared to baseline benchmarks

7
Board Layout
Power Terminal
-
-
-
-
-
-
-
-
-
-










64K x 18b SRAM 0
64K x 18b SRAM 2
64K x 18b SRAM 3
64K x 18b SRAM 1
64K x 18b SRAM 4
-

Altera FLEX 10K 10K70RC240
JTAG 10-pin
-
-
-
-
-
-
1






1
Resister Bank 1K
HCI Stuff
SCI 10-pin
-

MC68HC11
MAX323CPE
-
-


8MHz Crystal
8 DIP Switches
LEDs (10)
-
-
-
-




Resister Bank 1K
DM7400N
8
Mystery Machine
9
Architecture Description
Program Mem
HC11
Clk Divider
Mem
Memory Bus Controller
LCD/HCI HC11
LCD
Chess Piece Registers
Mem
Eval Unit
Attack/Check Unit
Gen Unit
10
Architecture Description
  • Two HC11s
  • One for Chess Functions
  • One for Human Interface
  • Shared Memory
  • Gen function depends shared memory
  • Memory requirements have changed
  • HCI inputs go thru FPGA
  • From switches to 2nd HC11

11
Implementation Strategy
  • Moved SW cycle-intensive functions to HW
  • Partitioned Problem Early
  • Split Tasks by Personal Interests of Group
    Members
  • Tasks shifted as Individual Abilities became
    Clearer

12
Integration Plan
Software/Profiling
HW/SW Partitioning
Baseline Stats
FPGAAttack
FPGAEval
FPGAGen
HW/SW Interface
SW modification / optimization
FPGAHCI
CoSim
Physical Design
Integration/Debugging
Optimizations
Baseline Stats
13
Original Profiling (Sparc)
  • In_check attack
  • 55 of program run time!
  • Straight forward for hardware
  • Eval related
  • 25 program run time!
  • Straight forward for hardware.
  • Gen related
  • 15 of program!

14
Profiling in HiWare
  • Eval related
  • 35
  • Gen related
  • 22
  • Attack inCheck
  • 10

15
Scooby
  • Matts Jobs
  • Get eval Function Working in Hardware
  • Get the Memory Working

Rut-Ro Raggy
16
Rook Logic
knight_pcsqlight_knight_650 0
bishop_pcsqlight_bishop_550 0
eval_light_pawn(light_pawn_050) 0
eval_light_pawn(light_pawn_150) 0
eval_light_pawn(light_pawn_250) 0
eval_light_pawn(light_pawn_350) 0
eval_light_pawn(light_pawn_450) 0
eval_light_pawn(light_pawn_550) 0
eval_light_pawn(light_pawn_650) 0
eval_light_pawn(light_pawn_750) 0
knight_pcsqlight_knight_150 0
bishop_pcsqlight_bishop_250 0
ht_rook_0_score 0
light_rook_7_score 0
piece_matLIGHT
pawn_matLIGHT
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
16bit 8-input Adder
16bit 8-input Adder
king_endgame_pcsq light_king53
eval_light_king (light_king53)
add
add
16
16
1 0
16
piece_matDARK lt 1200
scoreLIGHT
17
Eval Function
scoreDARK
16
scoreLIGHT
16
A - B subtract
A - B subtract
16
16
0 1
side
Output_score
18
Daphne or Velma?
  • Annies Responsibilities
  • Attack function in Hardware
  • Wire Wrapping Queen

I love wire wrapping!
???
19
Attack Pieces Implementation
  • If running attack on one square, why not on 128
    squares in parallel? or perhaps use a piece
    implementation for of attack table and only run
    it on 32 squares..
  • Acts as a lookup table for other functions

Board Implementation
Piece Implementation
64 times..
20
Attack Table Diagram
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Green attack table
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
B
N
R
K
R
0
0
0
0
0
0
1
0
B
0
0
0
0
0
0
0
0
P
P
N
Q
0
0
0
0
0
0
0
0
P
P
P
P
P
0
0
0
0
0
0
0
0
n
p
p
P
p
p
p
p
p
0
0
0
0
0
0
0
0
Red attack table
r
p
r
q
0
0
0
0
0
0
0
0
n
b
b
k
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
Green move
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B
N
R
K
R
B
0
0
0
0
0
0
0
0
P
P
N
Q
0
0
0
0
0
0
0
0
P
P
P
P
0
0
0
0
0
0
0
0
Red attack table
P
p
p
P
0
0
0
0
0
0
0
0
p
p
p
p
p
0
0
0
1
1
0
0
0
r
p
r
q
0
0
0
0
0
1
1
0
n
b
b
k
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
21
Attack Specifics
  • Construct two chess boards one for white pieces
    and one for black
  • Instead of a piece, each square would contain a
    true or false depending on whether the square was
    being attacked for that color piece
  • Every time a player makes a move, the attack
    function on the fpga, rebuilds the table

22
Shaggy
  • Jims Stuff to do
  • Move Generator in Hardware
  • Manage Spreadsheet of Pin Lists
  • Board Layout

Zoinks!
23
Move Generator
  • 6 Modules
  • Counter
  • Piece MUX
  • FSM
  • Adder
  • IsOccupied
  • Memory Pusher
  • 2 states for each type of move
  • Compute Next Square
  • Is Next Square Occupied?

24
Move Generator
Bits
Pieces
Color
FSM
Move
Memory Pusher
address
Position
Pieces
hold
M U X
data
Type
capture
start
Counter (0-15)
select
next
Color
25
Move Generator FSM
Start 0
R
Fs -8
FRs -7
Q,R
FLs -9
F -8
K,Q,B
K,Q
K,Q
Q,B
Q,B
Pawn Moves
FR -7
FL -9
B
alive
R
K,Q
BR 9
BL 7
Other Piece Moves
L -1
Ls -1
R 1
Rs 1
B 8
B
Q,R
Q,R
N
2FR -17
2FL -15
K,Q
N
Ls -1
R
R
K,Q
Rs 1
N
BR 9
BL 7
B
Bs 8
FL2 -10
FR2 -6
B 8
Q,B
Q,B
K,Q
K,Q
Knight Moves
BLs 7
BRs 9
N
Q,R
BL2 6
BR2 -10
Bs 8
N
B2L 15
B2R 17
N
N
Geepers!
N
Wait -31
26
Fred
  • Jeffs Tasks
  • Design Human Interface
  • Hardware Design
  • Implementation

I have an idea!
27
HCI - Hardware
  • Output
  • LCD Display (MEG12864)
  • Display Controller (KS0708)
  • Input
  • DIP Switches
  • Control
  • Second 68HC11

MEG12864 LCD Display
KS0708 Display Controller
Busy Signal
Display Data
68HC11
FPGA
28
HCI - Software
  • LCD control/display program
  • Controls the LCD display and the HCI FPGA
    interface

Write to DDRAM
DDRAM Completely Written
Initialize
Write More to DDRAM
Busy
Display DDRAM
Check Busy Flag
Busy
Initialized
Data Displayed Repeat...
........... .......... .......
. ....... ...... .. ........
...
Array ,, ,,
  • Utility program
  • Converts ASCII text file of s and .s into
    array for use by LCD control/display program

29
HCI - Problems Solutions
  • Timing discrepancies between HC11 (8 MHz) and
    display controller (450 kHz)
  • Needed to work in assembly level of code for HC11
    to determine clock cycles necessary for
    functions--inserted no-ops as needed to delay
    HC11 until display controller could respond
  • Busy signal requirement of LCD display
  • Needed to add extra code and to the functions to
    read from the LCD display to determine the status
    of the Busy signal before writing to DDRAM
  • Voltage requirements of LCD (8 different
    voltages)
  • Resistors used to get required voltages ranging
    from 5 V to -12 V
  • Non-availability of connector for LCD cable in
    quantities less than 10,000.
  • Quality time with a soldering iron and a
    magnifying glass to create a custom connector for
    the LCD display

30
Scrappy
  • Jons Responsibilities
  • Team Leader
  • Software and Co-Design
  • HC11 guru

Let me at em! Ill splat em!
Scooby Snacks!
31
The Co-Simulator
  • Threads are not required to make the thing work.
  • Try to keep inputs and outputs less than 32 bits.
    There is a work around, but it isnt the
    prettiest thing.
  • Good for verification of hardware design. We run
    both the Verilog simulation and the software
    baseline and compare for correctness.

32
Technical Lessons Learned
  • Hardware
  • Soldering and wire wrapping
  • Multimeters are our friends
  • The Logic Analyzer is the real Mystery Machine
  • Software
  • Differences in word size b/n HC11 and rest of
    world
  • Low-level Coding (C and Assembly)
  • Timing Issues (nops)

33
CAD Tools Lessons Learned
  • Verilog
  • casex (much cooler than regular case)
  • defines, ifdefs
  • Testing
  • Max-Plus II
  • Laying out Pins on FPGA before running Max-Plus
    II (the chicken and the egg)
  • Synplify
  • Graphical View (RTL and Technology views)

34
Project Lessons Learned
  • Sticking to a schedule is harder than it looks
  • Wake-up calls
  • Document Changes
  • Be Flexible
  • Yelling and throwing things sometimes helps
  • HW and SW have to cooperate
  • Beg your Mom for help
  • Pay attention to Demo 0

35
The Mystery
Who put the Altera on the ceiling?
I wonder how that got up there?
YIKES!
Groovy!
36
The Villain
I think I know who it is!
Fred unmasks the villain!
37
The Villain Unmasked!
And I would have succeeded if not for those
meddling kids!
Professor Paul!
38
Thanks!
Lets get out of here!
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