Electromagnetic FDTD simulation on FPGAs

1
Electromagnetic FDTD simulation on FPGAs

• Yury Markovisky
• cs294

2
Review

• EM simulations using FDTD
• Simple algorithm requiring large computing power
• Operation
• Update fields in order
• E-field updates
• H-field updates
• Notice similarities in structure

3
Single Datapath Unit

• Using single precision (32bit) FPs
• FP cores from eda.org
• Area 6756 Luts 8 Block Mults
• Freq 9.3 Mhz
• Pipeline/retime (12-cycles) 70Mhz
• Synplicity

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Complete Datapath
H
E
k
6
3
7
Approximate Area 21000 LUTs Memory Bandwidth
Limited 16 word input 3 word output
Ey
3
E
5
Basic Datapath
B0
B2
READ CTL
WRITE CTL
B1
B3
6
Compute E
B0
B2
H
E
READ CTL
WRITE CTL
B1
B3
H
E
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Compute H
B0
B2
H
E
READ CTL
WRITE CTL
B1
B3
H
E
8
Neighbor FPGA
B0
B2
Boundary E/H
READ CTL
WRITE CTL
B1
B3
Boundary E/H
Neighbor FPGA
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Issues

• Not bound by area, but by mem b/w
• Data layout
• Separate E/H
• Place kEs with Es and kHs with Hs
• Balance memory and b/w utilization between banks

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Programming

• Load/save data for the simulation
• Load material coefficients on-chip
• Initialize E/H fields
• Read results of the simulation
• Reading all N3 cells is impractical (slow and
  hard to visualize)
• Can read several plane cuts through the 3D space

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Data read/write
Ether/MGT
B0
B2
Boundary E/H
READ CTL
WRITE CTL
B1
B3
Boundary E/H
Neighbor FPGA
Ether/MGT
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Simple Scenario
Computer
Ether
FPGA1
FPGA2
5002 slice of Ex-field is 1Mbyte of data GigE
can pull greater than 100 samples/sec
FPGA3
FPGA4
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Conclusion/Status

• Todo
• Finish analysis of
• Data layout
• On-chip Memory requirements
• Static scheduling of operations
• Find/design SDRAM interface
• Find/design Ether/MGT interface for load/save of
  data
• Design read/write ctrl
• Design data exchange between chips.