Simulation and Testbench

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Simulation and Testbench

Nov. 3rd 2005
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Simulation
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Chip tester
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Test bench
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A Simple Test Bench
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Simulation result
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Using Assert Statement
Assert boolean-expression report
string-expression severity expression
The boolean-expression is evaluated and if the
expression is false, the string-expression
specified in report statement is displayed in the
simulator window. The severity statement then
indicates to the simulator what action should be
taken in response to the assertion
failure. Severity NOTE, WARNING, ERROR, FAILURE.
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Using Assert Example
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Simulation result
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continued
Wrong AND code
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Failed assert
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Can we change assert positions?
changed
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Simulation of wrong test bench
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Explain the simulation result
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Using Loop and Multiple Processes
data_in
data_out
clock
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Simulation results
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Using Test Vectors
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Simulation Results
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Reading and Writing Files
THE TEXTIO PACKAGE TEXTIO is a package of VHDL
functions that read and write text files. To make
the package visible use std.textio.all Data
Types text -- a file of character strings
line -- one string from a text file Example
Declarations    file Prog text is in
"file_name" --text file "file_name"   
variable L line              -- read lines
from file to L Reading Values From a
File readline --Read one line from "text" file
F to "line" L read --Read one value from "line"
L into variable VALUE Writing values to a
file writeline --Write one line to "text" file
F from "line" L   write --Write one value to
"line" L from variable VALUE
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Reading File Example
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Simulation Results
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Writing File Example
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Simulation Results
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Reading Assignment
Chapter 11 Model Simulation