Simulation

1
Firmware Design

• Simulation
• FPD DFE firmware has been tested using the Test
  Bench for Active-HDL.
• Test Vectors for have been passed.

• Implementation
• Initial firmware was implemented.
• No errors or major warnings in the implementation
  results.
• Code tested on February 2003.

2
Firmware Test

• CTS tests
• DFE firmware (15 sigma) was tested using Data
  Pump.
• AFE test vectors ready to go (Mario Vaz).

• Platform test
• None before I left.

3
Hardware

• DFE Boards
• 2 DFEs in place with LVDS cables, fibers
  (1/board) for L3 identified not yet plugged
• 3rd board being tested by Jamieson today

• Start-up
• Plan to leave DFE boards 1,3 plugged in
• Use board 2 for CTS tests

4
Cable Map
5
Firmware Future Plans

• CTS tests
• New DFE firmware test in Data Pump.
• New DFE firmware tested using the whole chain
  (AFE output DFE TM) .

• Platform test
• DFE ware data base update.
• AFE test vectors in platform.
• DFE test vectors in platform.
• TM communication test.
• Whole chain test.

6
Firmware Future Plans

• Brazil (Mario Wagner)
• Test Vectors.
• C routine to obtain TV for Data Pump.
• C routine to obtain TV for VHDL test bench.
• New set of equations
• New proposals for the firmware scheme.

• USA
• DFE test in place (Daniel).
• DFE firmware design (Daniel Ricardo).
• Simulation
• Implementation
• New proposals for the firmware scheme (Daniel
  Ricardo).

7
Firmware Future Plans

• Some Code Guidelines
• Since FPD DFE is going to have only one output to
  TM, it would be worth to think in using only one
  sender. All the information can be passed using
  the 8 bits wide bus available for inter-devices
  communication

• Some Test Guidelines
• Make sure that FPD DFE is working by using DFE
  ware.
• Test using test signals from Amplifier Shaper.
• Do the previous test for AFE, DFE and TM.