EECSCS 370

1
EECS/CS 370

• Pipelining
• Lecture 17

2
Pipelining questions

• How would you modify the pipeline datapath if you
  wanted to double the clock frequency?
• Would it actually double?
• How do you determine the frequency?

3
Sample Code (Simple)

• Run the following code on a pipelined datapath
• add 1 2 3 reg 3 reg 1 reg 2
• nand 4 5 6 reg 6 reg 4
  reg 5
• lw 2 4 20 reg 4 Memreg220
• add 2 5 5 reg 5 reg 2 reg 5
• sw 3 7 10 Memreg310 reg 7
• Also, think about modifications for JALR

4
M U X
1
target
PC1
PC1
0
R0
eq?

R1
regA
ALU result

R2
Register file
regB
valA
M U X
PC
Inst mem
Data memory
instruction

R3
ALU result
mdata

R4
valB

R5

R6
M U X
data

R7
offset
dest
valB
Bits 0-2
dest
dest
dest
Bits 16-18
M U X
Bits 22-24
op
op
op
IF/ ID
ID/ EX
EX/ Mem
Mem/ WB
5
M U X
1
0
0
0
0
R0
0
36
R1
0
9
R2
Register file
0
M U X
PC
Inst mem
Data memory
noop
12
R3
0
0
18
R4
0
7
R5
41
R6
M U X
data
22
R7
0
dest
0
Initial State
Bits 0-2
0
0
0
Bits 16-18
M U X
Bits 22-24
noop
noop
noop
IF/ ID
ID/ EX
EX/ Mem
Mem/ WB
6
add 1 2 3
M U X
1
0
0
1
0
R0
0
36
R1
0
9
R2
Register file
0
M U X
PC
Inst mem
Data memory
add 1 2 3
12
R3
0
0
18
R4
0
7
R5
41
R6
M U X
data
22
R7
0
dest
0
Fetch add 1 2 3
Bits 0-2
0
0
0
Bits 16-18
M U X
Bits 22-24
noop
noop
noop
IF/ ID
ID/ EX
EX/ Mem
Mem/ WB
Time 1
7
nand 4 5 6 add 1 2 3
M U X
1
0
1
2
0
R0
0
36
R1
1
0
9
R2
Register file
36
2
M U X
PC
Inst mem
Data memory
nand 4 5 6
12
R3
0
0
18
R4
9
7
R5
41
R6
M U X
data
22
R7
3
dest
0
Fetch nand 4 5 6
Bits 0-2
3
0
0
Bits 16-18
M U X
Bits 22-24
add
noop
noop
IF/ ID
ID/ EX
EX/ Mem
Mem/ WB
Time 2
8
lw 2 4 20 nand 4 5 6 add 1 2 3
M U X
3
1
4
1
2
3
0
R0
0
36
R1
4
0
36
9
R2
Register file
18
5
M U X
PC
Inst mem
Data memory
lw 2 4 20
12
R3
45
0
18
R4
9
7
7
R5
41
R6
M U X
data
22
R7
6
dest
9
Fetch lw 2 4 20
Bits 0-2
3
6
3
0
Bits 16-18
M U X
Bits 22-24
nand
add
noop
IF/ ID
ID/ EX
EX/ Mem
Mem/ WB
Time 3
9
add 2 5 5 lw 2 4 20 nand 4 5
6 add 1 2 3
M U X
6
1
8
2
3
4
0
R0
0
36
R1
2
45
18
9
R2
Register file
9
4
M U X
PC
Inst mem
Data memory
add 2 5 8
12
R3
-3
0
18
R4
45
7
18
7
R5
41
R6
M U X
data
22
R7
20
dest
7
Fetch add 2 5 5
Bits 0-2
3
6
4
6
3
Bits 16-18
M U X
Bits 22-24
lw
nand
add
IF/ ID
ID/ EX
EX/ Mem
Mem/ WB
Time 4
10
sw 3 7 10 add 2 5 5 lw 2 4
20 nand 4 5 6 add
M U X
20
1
23
3
4
5
0
R0
0
45
36
R1
2
-3
9
9
R2
Register file
9
5
M U X
PC
Inst mem
Data memory
sw 3 7 10
45
R3
29
0
18
R4
-3
7
7
R5
41
R6
M U X
data
22
R7
20
5
dest
18
Fetch sw 3 7 10
Bits 0-2
6
3
4
5
4
6
Bits 16-18
M U X
Bits 22-24
add
lw
nand
IF/ ID
ID/ EX
EX/ Mem
Mem/ WB
Time 5
11
sw 3 7 10
add 2 5 5 lw 2 4 20 nand
M U X
5
1
9
4
5

0
R0
0
-3
36
R1
3
29
9
9
R2
Register file
45
7
M U X
PC
Inst mem
Data memory
45
R3
16
99
18
R4
29
7
22
7
R5
-3
R6
M U X
data
22
R7
10
dest
7
No more instructions
Bits 0-2
4
6
5
7
5
4
Bits 16-18
M U X
Bits 22-24
sw
add
lw
IF/ ID
ID/ EX
EX/ Mem
Mem/ WB
Time 6
12

sw 3 7 10 add 2 5 5 lw
M U X
10
1
15
5


0
R0
0
36
R1

16
45
9
R2
Register file


M U X
PC
Inst mem
Data memory
45
R3
99
55
0
99
R4
16

7
R5
-3
R6
M U X
data
22
R7
10

dest
22
No more instructions
Bits 0-2
5
4
7

7
5
Bits 16-18
M U X
Bits 22-24

sw
add
IF/ ID
ID/ EX
EX/ Mem
Mem/ WB
Time 7
13

sw 3 7 10
add
M U X
1



0
R0

16
36
R1

55
9
R2
Register file


M U X
PC
Inst mem
Data memory
45
R3

0
99
R4
22
55

16
R5
-3
R6
M U X
data
22
R7

dest
22

No more instructions
Bits 0-2
5


7
Bits 16-18
M U X
Bits 22-24


sw
IF/ ID
ID/ EX
EX/ Mem
Mem/ WB
Time 8
14


sw
M U X
1



0
R0

36
R1


9
R2
Register file


M U X
PC
Inst mem
Data memory
45
R3


99
R4

16
R5
-3
R6
M U X
data
22
R7

dest

No more instructions
Bits 0-2



Bits 16-18
M U X
Bits 22-24



IF/ ID
ID/ EX
EX/ Mem
Mem/ WB
Time 9
15
Time graphs
Time 1 2 3 4
5 6 7 8 9
add nand lw add sw
fetch decode execute memory writeback
fetch decode execute memory writeback
fetch decode execute memory writeback
fetch decode execute memory writeback
fetch decode execute memory writeback
16
What can go wrong?

• Data hazards since register reads occur in stage
  2 and register writes occur in stage 5 it is
  possible to read the wrong value if is about to
  be written.
• Control hazards A branch instruction may change
  the PC, but not until stage 4. What do we fetch
  before that?
• Exceptions How do you handle exceptions in a
  pipelined processor with 5 instructions in flight?