A PathBased Methodology for PostSilicon Timing Validation

1
A Path-Based Methodology for Post-Silicon Timing
Validation

• Leonard Lee1, Li-C. Wang1,
• T.M. Mak2, and Kwang-Ting Cheng1
• 1 Department of ECE, UC-Santa Barbara
• 2 Intel Corporation, Santa Clara, CA

2
Outline

• Motivation introduction
• Methodology
• Post-silicon path ranking
• Path filtering
• Ranking optimization
• Experimental results
• Conclusion

3
Motivation

• Variations and uncertainty with DSM
• Harder design and production
• Statistical timing approaches
• Promise to cope better
• But
• Are we sure about our statistical timing models?
• Resolve some problems in post-silicon
• Learn from silicon test chips

4
Silicon test chip driven

• We call it Silicon Learning
• Patterns applied to test chips
• Uses observed silicon behavior to learn design
  parameters
• In this paper, we define the Path Ranking
  Optimization problem
• As an example of this silicon learning framework
• One application timing validation
• Compare post-silicon based path ranking to path
  ranking calculated from the timing model

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Silicon Learning

• Silicon Learning Framework
• Find best hypothesis to explain observed behavior
• Generic can be applied in many cases
• Facilitate silicon-based test methods
• Does not reveal exactly what the error is
• Instead provides information like path ranking

A hypothesis on model parameters
Model simulation
Predicted behavior
A way to define the difference between the two
error to be minimized
Observed behavior from silicon
A typical silicon learning problem formulation
The objective is to find the best hypothesis to
minimize the error
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An example of Silicon Learning

• Post-silicon path ranking
• Hypothesize on path delays from observed pattern
  delays
• Ranking optimization
• From hypothesis
• Compute pattern delays via path sensitization
• Compare observed and computed pattern delays
• Before applying this learning, we need to have a
  Path Filtering step to reduce the search space

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Outline

• Motivation introduction
• Methodology
• Post-silicon path ranking
• Path filtering
• Ranking optimization
• Experimental results
• Conclusion

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Post-silicon path ranking
.
M patterns

N sample chips

• Given the pass/fail data on a set of patterns
• Is this behavior expected by the timing model?
• If not expected by statistical timing
• Where is the problem?
• Cant trust timing analysis and simulation
• Based on timing model
• We can trust (based solely on circuit structure)
• Logic simulation
• Logic path sensitization

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The overall methodology
A set of long paths
Post-silicon path ranking
Silicon Path Ranking
SSTA
Statistical important paths
Path Filtering
A pattern set
Compare
SSTA
pass/fail data
Sample chips
Pre-silicon path ranking
patterns delays
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Path-based learning
Paths 1 2 3 4 5 . K
delays
Pattern 1
X X X
?
0.9ns
Estimated path delays that better match
the observed patterns delays
Pattern 2
X X X

1.05ns

X X
0.85ns
Pattern M

• Given set of paths and set of patterns
• Map logic path sensitization to observed pattern
  behavior
• If the problem space is too large (too many
  paths)
• Path filtering
• Based on Support Vector Machine (SVM)
• Use the approach proposed in DAC 2004
• Formulate problem as an error minimization
  problem
• Greedy heuristic
• Ranking Optimization

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More about patterns

• Pattern delays are distributions
• The learning can be applied at many different
  points
• In this work, we focus on learning the average
  delay
• The framework can be applied to learn 3sigma
  delay or any other points of delay
• The complexity of learning
• Trivial if 1 to 1 mapping exists between a
  pattern and a path
• In our application, a pattern may sensitize many
  paths
• So that the learning is not biased toward a small
  number of paths
• So that the learning framework can be applied
  with any type of patterns, such as functional
  patterns

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Outline

• Motivation introduction
• Methodology
• Post-silicon path ranking
• Path filtering
• Ranking optimization
• Experimental results
• Conclusion

13
Path filtering

• For details, refer to
• Li-C. Wang, et. al. On Path-based Learning and
  Its Applications in Delay Test and Diagnosis. in
  Proc. ACM/IEEE DAC, June 2004
• Given m patterns and n samples
• Construct a learned model using SVM
• Patterns divided by failure probability into two
  groups
• Binary classification
• The objective is to extract patterns which are
  critical to derive the learned model
• Then, we can find paths critical in
  differentiating the two groups
• Derive SV critical paths
• These paths are those most relevant to the
  observed behavior

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Outline

• Motivation introduction
• Methodology
• Post-silicon path ranking
• Path filtering
• Ranking optimization
• Experimental results
• Conclusion

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Ranking Optimization
Paths x y z
delays
?
delay of x 0.8ns gt Pattern 2 0.8ns delay of y
(unknown) delay of z 1.0ns gt Pattern 1 1.0ns
Pattern 1
X X
1.0ns
Pattern 2
X
0.6ns

• Problem several patterns sensitize a path
• Initially path receives equal effect from all
  patterns
• Possible scenario
• Path x has a short delay
• What if a pattern with a long delay sensitizes x?
• Pattern that sensitizes only x has its delay
  overestimated
• Estimated error of pattern i (erri)
• Difference between calculated pattern delay and
  observed pattern delay
• Total estimated error ?i erri

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Ranking Optimization

• To minimize total estimated error
• Weights on pattern delay
• Change hypothesized path delay by changing
  weights
• Begin with 1, 1, , 1 (equal effect)
• Each iteration
• Find largest estimated error
• Random choice from the top 5 erri
• Increase the weight
• wi ? wi ? x erri

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Effectiveness

• Compares estimated error with true error
• In practice, true error is not known (path based
  error)
• Estimated error tracks true error well
• They follow similar trends
• Quickly converges, 50 iterations is more than
  sufficient

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Outline

• Motivation introduction
• Methodology
• Post-silicon path ranking
• Path filtering
• Ranking optimization
• Experimental results
• Conclusion

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Experimental tools and setup

• Use a Statistical STA to extract a set of
  potentially critical paths
• This is the initial path set
• Use a Monte-Carlo based statistical pattern-based
  timing simulator
• Emulate application of patterns on test chips
• Conduct two types of experiments
• SSTA and simulator use the same timing model
• SSTA and simulator use different timing models

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Path ranking analysis

• Without path filtering, we have a large number of
  paths to begin with
• It is hard for path ranking optimization alone to
  derive the good correlation
• In this case, SSTA and simulator use the same
  model

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After path filtering

• Better resolution with SVM-based path extraction
  (left)
• SV path removal can further reduce the noise
  (right)
• The remaining paths can be used for diagnosis
• In this case, post-silicon path ranking
  correlates to the pre-silicon SSTA ranking
• SSTA and the simulator use the same timing model

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Not correlated

• Change SSTA timing model by using only
• Rising delay distributions
• Falling delay distributions
• In simulation (for producing sample chip
  results), we assume the original timing model

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More results
c2670
s5378
Same timing model
Use only rising delays
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Outline

• Motivation introduction
• Methodology
• Post-silicon path ranking
• Path filtering
• Ranking optimization
• Experimental results
• Conclusion

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Conclusion

• Using information inferred from silicon behavior
• Silicon learning generic framework for inference
• Path ranking correlate between silicon and model
• Path filtering
• Too many paths introduce noise due to
  co-sensitization
• Use SVM to reduce path set
• Ranking optimization
• Use to improve hypothesis on path delays
• Silicon learning does not provide 100 answers
• With limited knowledge about the internal
  behavior of sample chips, path delays cannot be
  inferred 100 correctly