CSC Muon Sorter

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CSC Muon Sorter Status Tests Plans M.Matveev A
ugust 21, 2003
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Muon Sorter Board
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Status
Have one assembled MS board with a mezzanine
FPGA Three other boards have been assembled
and partially tested without mezzanines Have a
dedicated test stand - 9U crate with Track
Finder Backplane - MS with mezzanine FPGA
- Clock and Control Board - SBS 620 VME
controller - Linux PC
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Hardware/Firmware Tests
VME Access to FPGA and JTAG controller was
checked. Extensive tests of sorting logic
and LUTs Front panel connection to GMT was
verified with a loopback cable
FPGA
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VME/JTAG Interface
XILINX PARALLEL CABLE
TDI TCK TMS
Xilinx XC2V4000 mezzanine FPGA and associated
EPROMs may be loaded/programmed from Xilinx
Parallel Cable IV Fairchild SCANPSC100F JTAG
controller under VME control
MUX
TDO
FAIRCHILD SCANPSC100
XILINX FPGA
XILINX PLD
VME
National Semiconductor provides a free software
to operate SCANPSC100F controller, that was
adopted by UF to work via VME using SBS 620
Master.
We have successfully run this software to
program 4 EPROMs residing on the mezzanine
card Program time is 1 min (4 min over Xilinx
Parallel Cable IV)
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FPGA Latency
F45 Mhz
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Tests with Sector Processor
For initial tests we need one Sector Processor
with mezzanine FPGA installed and minimal
firmware Output 51232 memory buffer for data
to be sent to MS Input 5122 memory buffer for
winner bits from MS Memory buffers can be
either FIFOs or dual-port RAMs. Both must be
under VME control. Verilog implementation of the
dual-port RAM can be borrowed from the TMB
design and adopted for SP.
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Plans
Continue bench testing when SP is available
Data consistency check Winner logic
Latency Tests with Global Muon
Trigger Integrated test of the peripheral/TF
electronics