Status of CSC Trigger

1
Status of the CSC Track-Finder D.Acosta,
A.Madorsky, S.M.Wang University of
Florida B.Cousins, J.Hauser, J.Mumford,
B.Tannenbaum University of California, Los
Angeles M.Matveev, T.Nussbaum, B.P.Padley Rice
University A.Atamanchouk, V.Golovtsov,
B.Razmyslovich, V.Sedov St. Petersburg Nuclear
Physics Institute
2
Outline

• Results of CSC Track-Finder Crate Tests
• Future RD
• Status of CSC Trigger Simulation
• Future Algorithm Improvements

3
Level-1 Trigger Architecture
12 Sector Processors
From DT Track-Finder
MB1
DT TF
(Vienna)
1 Muon Sorter
SP
ME4
(Vienna)
OPTICAL
ME2-ME3
To Global Muon Trigger
ME1
SR
MS
3? / sector
PC
Muon Port Cards
SP
36 Sector Receivers
12 sectors
GMT
4?
3? / port card
4?
(Florida)
(Rice)
(UCLA)
(Rice)
From DT Track-Finder
8?
RPC
4
Tests of Current Prototypes

• Prototypes of all Track-Finder components (except
  the CSC Muon Sorter) have been constructed
• Sector Processor UFlorida
• Sector Receiver UCLA
• Muon Port Card Rice
• Clock and Control Board Rice
• Channel-Link backplane UFlorida
• All boards were completed in July
• Since the last CMS week, we have focused on
  completing integration tests of the complete
  system

5
Sector Processor Prototype
Extrapolation Units XCV400BG560
Final Selection Unit XCV150BG352
Florida
12 layers 10K vias 17 FPGAs 12 SRAMs 25 buffers
Bunch Crossing Analyzer XCV50BG256
Track Assemblers 256k x 16 SRAM
Assignment Units XCV50BG256 2M x 8 SRAM
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Sector Receiver Prototype
Optical Receivers and HP Glinks
SRAM LUTs
UCLA
Front FPGAs
Back FPGAs
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Track-Finder Crate Tests
SP
SR
CCB
MPC
Bit3 VME Interface
Custom backplane
100m optical fibers
8
Test Results Sector Processor

• VME Interface
• All LUTs and FPGA programs downloaded in less
  than 30s through SBS Bit3 PCI to VME interface
• JTAG serialized on board _at_ 25 MHz
• Functionality
• Internal dynamic test _at_ 40 MHz works with 100
  agreement with ORCA simulation
• 180K single muons (and 60K triple muons)
• Internal FIFOs are 256 b.x. deep
• Latency is 15 b.x. (not including Channel-Link
  input)
• Firmware updated to latest (last weeks) ORCA
  algorithms
• CSC region works flawlessly, but still working
  on DT/CSC overlap region
• Plan to test even larger data samples (and
  random data) to look for any rare errors

9
Test Results Sector Receiver

• Functionality
• Three boards built and tested
• Internal dynamic test _at_ 40 MHz works with ORCA
  data and pseudo-random data
• Tested 30K cycles of 256 random events
• Some rare (10-6) errors encountered and under
  study
• One board with slower SRAM (10ns vs. 8ns) works
  fine even with 2 memories cascaded with 25 ns
  clock
• Emulation software is similar to ORCA, but not
  same code
• Although LUT contents were generated from ORCA

10
System Tests Done in Last Month

• Port Card ? Sector Receiver
• MPC and SR communicate via HP GLinks and optical
  fiber
• Data successfully sent from input of one MPC,
  through 100m of optical cables, to output of SR
• 1.6M random events processed with no errors
• Sector Receiver ? Sector Processor
• SR and SP communicate via Channel-Link backplane
• Data successfully sent from input of one SR,
  through custom backplane, into the SP
• Some errors encountered from unmasked inputs,
  but tracks were reconstructed correctly from the
  SR input
• Successfully sent data from three SRs connected
  to the SP to emulate an entire trigger sector

11
System Tests (Continued)

• Port Card ? Sector Receiver ? Sector Processor
• Successfully sent data from the input of two
  MPCs (representing ME2 and ME3), through one SR,
  and reconstructed tracks correctly in the SP
• Complete chain test
• The Clock and Control Board prototype coordinated
  these tests
• Distributed clock and control signals with
  programmable delays
• Sent BC0 to initiate tests
• Lots of software had to be developed (and
  coordinated between institutes) for these tests
  to happen

12
Future Plans Backplane

• We plan to replace Channel-Link transmission as
  much as possible from the CSC trigger path
  because of its long latency (3.5 b.x.)
• In particular, for the custom point-to-point
  backplane in the Track-Finder crate (and probably
  the front-end peripheral crates)
• Florida proposal is to use GTLP at 80 MHz
• Doubled frequency achieves 2? signal reduction
  (vs. 3? from Channel-Link)
• Can be bussed (although we plan point-to-point)
• No differential signals (fewer traces)
• Can be driven by Xilinx Virtex I/O directly,
  or from driver chips by Fairchild and TI
• Prototype backplane successfully tested in Florida

13
GTLP Test Fixture
Clock generator (160 MHz)
Virtex, or Fairchild GTLP16612
AMP Z-pack 2-mm 5-row
Backplane connector
Pattern generator
GTLP transmitter
Shift register
Comparator
GTLP receiver
50 ? Backplane traces (220 mm)
Error counter and display
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GTLP Backplane Tests
Alternating and random patterns driven up to 160
MHz with no errors
Virtex
Drivers
Backplane traces
80 MHz signal
160 MHz signal
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Future A Compact Muon Trigger

• Current technology will allow us to merge all 17
  FPGAs of prototype Sector Processor into just
  one
• Xilinx Virtex XCV2000E (2.5M gates) available
  now
• or Virtex 2, available soon
• This opens the possibility of merging the Sector
  Processor and Sector Receivers onto a single
  board
• Would allow for a single crate Track-Finder
  (currently 6)
• Reduces latency (up to 10 b.x.)
• No Channel-Link connection between SR and SP
• No cable to Muon Sorter
• Would allow communication between sectors
  (through backplane) to cancel ghost tracks at
  boundaries
• Under investigation by Florida
• Depends on new optical link technology to reduce
  connections from peripheral crate
• 1.6 Gbit links with 80 MHz clock
• Under investigation by Rice

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Possible Board Layout
17
Possible Crate Layout
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State of the Track-Finder Simulation

• It is working in ORCA 4.3.0 !
• PT assignment has been re-tuned on CMSIM118 and
  parameterized by a set of functions
• This offers flexibility
• PT binning may be changed
• 50 or 90 thresholds (or anything else) can be
  used
• Look-up table contents are still based on
  integers like hardware
• Contents computed dynamically
• Recent problem with PT assignment at ??1.5 fixed
• L1 Ntuples re-made thanks to Norbert
• Rate under control there, but still under study
  in DT/CSC overlap region
• All SW and HW algorithms tested and agree
• Modifications made to ORCA to match prototype
  exactly, and all LUTs used by HW generated from
  ORCA code

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CSC Trigger Efficiency vs. Eta
Any 2 stations
ME1 or MB1 any station
ME1 or MB1 any 2 stations
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PT Resolution and Efficiency
5 lt PT lt 50 GeV 1.2 lt ? lt 2.0
90 Efficiency Threshold
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CSC Trigger Rate
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PT Assignment Improvements

• Precision
• Current SP prototype performs a 3-station PT
  measurement using a 2 MB SRAM
• 27 resolution up to 35 GeV (20 for PT lt 5
  GeV)
• Resolution can improve further with 1 or 2 more
  bits of precision on ??23
• 22 resolution up to 35 GeV
• Use larger SRAM or multiple chips
• Likewise, anticipated improvements on ?
  resolution in CLCT and SR should extend this
  resolution up to 50 GeV
• Stronger background rejection, higher efficiency
• DT/CSC Overlap
• Tracks bend back between MB1 and ME2 at low PT
• Ambiguity in assigning PT based on ??
• Will investigate using ?bend and ??12 for PT
  assignment in place of 3-station measurement for
  this region
• Wont help tracks without MB1
• No bending between ME1 and ME2

23
Conclusions

• Prototype tests were a success (but a lot of
  work)
• It was a useful exercise to commission a crate of
  trigger electronics
• Validates the trigger architecture
• Gives us some idea of what to expect when we
  commission the real system
• Learned of some (solvable) incompatibilities
• Different VME addressing conventions
• Different patterns and sorting logic than
  expected
• Provides guidance on how to improve future
  boards
• Additional VME registers to set board functions
  or to spy on intermediate data
• ORCA software is basically in shape for the TDR
• Expected efficiency and rate reduction achieved
  in endcap
• Still expect future improvements and tuning to
  occur