A Delay Line Based DesignforTest Technique for Sinusoidal Jitter Measurement

1
A Delay Line Based Design-for-Test Technique for
Sinusoidal Jitter Measurement

• C.-Y. Kuo and J.-L. Huang
• Department of Electrical Engineering
• National Taiwan University

2
Motivation

• Different jitter components have different
  impacts on a transmission system, such as PLLs.
• Low frequency drift is more tolerable.
• The same amount of random jitter can be
  catastrophic.
• Characteristics of the total jitter is often
  misleading and inaccurate.
• Jitter decomposition is essential in
  communication system testing and diagnosis.
• SJ extraction

3
The Sinusoidal Jitter Extraction Circuit

• Force the delay line value to track the period
  variation.

• Store the delay value sequence.
• Post processing for SJ extraction.

4
Conclusion

• An on-chip SJ extraction technique is proposed.
• Based on the period tracking algorithm.
• With a variable delay line and a phase
  comparator.
• Simulations show that high amplitude and
  frequency estimation accuracies can be achieved.
• Robust in the presence of random jitter
  components.